ICV_HPPIR1_EL1 Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1 when GICv3 is implemented, EL2 is implemented, and FEAT_AA64 is implemented ICV_HPPIR1 Functional AArch32 31 0 31 0 31 0 31 0 Indicates the highest priority pending virtual Group 1 interrupt on the virtual CPU interface. GICV Control GIC ICV_HPPIR1_EL1 is a 64-bit register. 63 24 63:24 Reserved, RES0. INTID 23 0 23:0 The INTID of the highest priority pending virtual interrupt. If the highest priority pending interrupt is not observable, this field contains a special INTID to indicate the reason. This special INTID can take the value 1023 only. For more information, see 'Special INTIDs' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICV_CTLR_EL1.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0. MRS <Xt>, ICC_HPPIR1_EL1 if !(IsFeatureImplemented(FEAT_GICv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().IRQ == '1' then Undefined(); elsif ICC_SRE_EL1().SRE == '0' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TALL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then X{64}(t) = ICV_HPPIR1_EL1(); elsif HaveEL(EL3) && SCR_EL3().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ICC_HPPIR1_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().IRQ == '1' then Undefined(); elsif ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ICC_HPPIR1_EL1(); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else X{64}(t) = ICC_HPPIR1_EL1(); end; end; 2026-03-26 20:27:25 2026-03_rel