ID_AA64DFR0_EL1 AArch64 Debug Feature Register 0 when FEAT_AA64 is implemented Provides top-level information about the debug system in AArch64 state. For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'. Identification Registers The external register EDDFR gives information from this register. ID_AA64DFR0_EL1 is a 64-bit register. HPMN0 63 60 63:60 Zero PMU event counters for a Guest operating system. All other values are reserved. FEAT_HPMN0 implements the functionality identified by the value 0b0001. From Armv8.8, in an implementation that includes FEAT_PMUv3, FEAT_FGT, and EL2, the value 0b0000 is not permitted. 0b0000 Setting MDCR_EL2.HPMN to zero has CONSTRAINED UNPREDICTABLE behavior. 0b0001 Setting MDCR_EL2.HPMN to zero has defined behavior. RO ExtTrcBuff 59 56 59:56 Trace Buffer External Mode Extension. All other values are reserved. FEAT_TRBE_EXT implements the functionality identified by the value 0b0001. 0b0000 Trace Buffer External Mode not implemented. 0b0001 Trace Buffer External Mode implemented. RO BRBE 55 52 55:52 Branch Record Buffer Extension. All other values are reserved. FEAT_BRBE implements the functionality identified by the value 0b0001. FEAT_BRBEv1p1 implements the functionality identified by the value 0b0010. From Armv9.3, if FEAT_BRBE is implemented, the value 0b0001 is not permitted. 0b0000 Branch Record Buffer Extension not implemented. 0b0001 Branch Record Buffer Extension implemented. 0b0010 As 0b0001, and adds support for branch recording at EL3. RO MTPMU 51 48 51:48 Multi-threaded PMU extension. All other values are reserved. FEAT_MTPMU implements the functionality identified by the value 0b0001. From Armv8.6, in an implementation that includes FEAT_PMUv3, the value 0b0000 is not permitted. In an implementation that does not include FEAT_PMUv3, the value 0b0001 is not permitted. 0b0000 FEAT_MTPMU not implemented. If FEAT_PMUv3 is implemented, it is IMPLEMENTATION DEFINED whether PMEVTYPER<n>_EL0.MT and PMEVTYPER<n>.MT are read/write or RES0. 0b0001 FEAT_MTPMU and FEAT_PMUv3 implemented. PMEVTYPER<n>_EL0.MT and PMEVTYPER<n>.MT are read/write. When FEAT_MTPMU is disabled, the Effective values of PMEVTYPER<n>_EL0.MT and PMEVTYPER<n>.MT are 0. 0b1111 FEAT_MTPMU not implemented. If FEAT_PMUv3 is implemented, PMEVTYPER<n>_EL0.MT and PMEVTYPER<n>.MT are RES0. RO TraceBuffer 47 44 47:44 Trace Buffer Extension. All other values are reserved. FEAT_TRBE implements the functionality identified by the value 0b0001. FEAT_TRBEv1p1 implements the functionality identified by the value 0b0010. In any Armv9 implementation, if FEAT_ETE is implemented, the value 0b0000 is not permitted. From Armv9.6, if FEAT_TRBE is implemented, the value 0b0001 is not permitted. 0b0000 Trace Buffer Extension not implemented. 0b0001 Trace Buffer Extension implemented. 0b0010 As 0b0001, and adds: If EL2 and FEAT_FGT are implemented, a fine-grained trap on the TSB CSYNC instruction. If EL2 is implemented, an EL2 control to override TRBLIMITR_EL1.nVM. The TRBE Profiling exception extension, FEAT_TRBE_EXC. RO TraceFilt 43 40 43:40 Armv8.4 Self-hosted Trace Extension version. All other values are reserved. FEAT_TRF implements the functionality identified by the value 0b0001. From Armv8.4, if FEAT_ETMv4 is implemented, the value 0b0000 is not permitted. If FEAT_ETE is implemented, the value 0b0000 is not permitted. 0b0000 Armv8.4 Self-hosted Trace Extension not implemented. 0b0001 Armv8.4 Self-hosted Trace Extension implemented. RO DoubleLock 39 36 39:36 OS Double Lock implemented. All other values are reserved. FEAT_DoubleLock implements the functionality identified by the value 0b0000. In Armv8.0, the only permitted value is 0b0000. If FEAT_Debugv8p2 is implemented and FEAT_DoPD is not implemented, the permitted values are 0b0000 and 0b1111. If FEAT_DoPD is implemented, the only permitted value is 0b1111. 0b0000 OS Double Lock implemented. OSDLR_EL1 is RW. 0b1111 OS Double Lock not implemented. OSDLR_EL1 is RAZ/WI. RO PMSVer 35 32 35:32 Statistical Profiling Extension version. All other values are reserved. FEAT_SPE implements the functionality identified by the value 0b0001. FEAT_SPEv1p1 implements the functionality identified by the value 0b0010. FEAT_SPEv1p2 implements the functionality identified by the value 0b0011. FEAT_SPEv1p3 implements the functionality identified by the value 0b0100. FEAT_SPEv1p4 implements the functionality identified by the value 0b0101. FEAT_SPEv1p5 implements the functionality identified by the value 0b0110. From Armv8.5, if FEAT_SPE is implemented, the value 0b0001 is not permitted. From Armv8.7, if FEAT_SPE is implemented, the value 0b0010 is not permitted. From Armv8.8, if FEAT_SPE is implemented, the value 0b0011 is not permitted. From Armv8.9, if FEAT_SPE is implemented, the value 0b0100 is not permitted. From Armv9.6, if FEAT_SPE is implemented, the value 0b0101 is not permitted. 0b0000 Statistical Profiling Extension not implemented. 0b0001 Statistical Profiling Extension implemented. 0b0010 As 0b0001, and adds: Support for the Events packet Alignment flag. If FEAT_SVE is implemented, support for the Scalable Vector extensions to Statistical Profiling. 0b0011 As 0b0010, and adds: Discard mode. Extended event filtering, including the PMSNEVFR_EL1 System register. Support for the OPTIONAL previous branch target Address packet. If FEAT_PMUv3 is implemented, controls to freeze the PMU event counters after an SPE buffer management event occurs. If FEAT_PMUv3 is implemented, the SAMPLE_FEED_BR, SAMPLE_FEED_EVENT, SAMPLE_FEED_LAT, SAMPLE_FEED_LD, SAMPLE_FEED_OP, and SAMPLE_FEED_ST PMU events. 0b0100 As 0b0011, and adds: If FEAT_MOPS is implemented, Operation Type packet encodings for Memory Copy and Set operations. If FEAT_MTE is implemented, Operation Type packet encodings for loads and stores of Allocation Tags. 0b0101 As 0b0100, and adds: Support for the Events packet Level 2 Data cache access, Level 2 Data cache miss, Cached data modified, Recently fetched cache line, and Cache snoop flags. Support for Data Source filtering. 0b0110 As 0b0101, and adds: If EL2 and FEAT_FGT are implemented, a fine-grained trap on the PSB CSYNC instruction. The SPE Profiling exception extension, FEAT_SPE_EXC. The Statistical Profiling physical addressing mode extension, FEAT_SPE_nVM. RO CTX_CMPs 31 28 31:28 Number of context-aware breakpoints, minus 1. Values greater than ID_AA64DFR0_EL1.BRPs are not permitted. If AArch32 is supported at EL1, then the PE does not implement more than 16 breakpoints. 0b0000..0b1110 The number of context-aware breakpoints, minus 1. 0b1111 If ID_AA64DFR1_EL1.CTX_CMPs is zero, then 16 context-aware breakpoints are implemented. Otherwise, 16 or more context-aware breakpoints are implemented and ID_AA64DFR1_EL1.CTX_CMPs indicates how many. RO 27 24 27:24 Reserved, RES0. WRPs 23 20 23:20 Number of watchpoints, minus 1. If FEAT_Debugv8p9 is implemented and 16 or more watchpoints are implemented, then this field reads as 0b1111 and ID_AA64DFR1_EL1.WRPs indicates the number of watchpoints. If AArch32 is supported at EL1, then the PE does not implement more than 16 watchpoints.The value 0b0000 is reserved. 0b0001..0b1111 The number of watchpoints, minus 1. RO PMSS 19 16 19:16 PMU Snapshot extension. All other values are reserved. FEAT_PMUv3_SS implements the functionality identified by the value 0b0001. 0b0000 PMU snapshot extension not implemented. 0b0001 PMU snapshot extension implemented. RO BRPs 15 12 15:12 Index of the highest numbered context-aware breakpoint. Identifies which of the implemented breakpoints are context-aware breakpoints. If ID_AA64DFR1_EL1.BRPs is zero, then this is also the number of implemented breakpoints, minus 1, meaning the context-aware breakpoints are the highest numbered breakpoints. The value of this field is always less than the number of implemented breakpoints. If AArch32 is supported at EL1, then the PE does not implement more than 16 breakpoints.The value 0b0000 is reserved. 0b0001..0b1110 Index of the highest numbered context-aware breakpoint. 0b1111 If ID_AA64DFR0_EL1.CTX_CMPs and ID_AA64DFR1_EL1.CTX_CMPs indicate that 16 or fewer breakpoints are context-aware, then the index of the highest context-aware breakpoint is 15. Otherwise, the context-aware breakpoints are the lowest numbered breakpoints. RO PMUVer 11 8 11:8 Performance Monitors Extension version. This field does not follow the standard ID scheme, but uses the alternative ID scheme described in 'Alternative ID scheme used for the Performance Monitors Extension version'. All other values are reserved. FEAT_PMUv3 implements the functionality identified by the value 0b0001. FEAT_PMUv3p1 implements the functionality identified by the value 0b0100. FEAT_PMUv3p4 implements the functionality identified by the value 0b0101. FEAT_PMUv3p5 implements the functionality identified by the value 0b0110. FEAT_PMUv3p7 implements the functionality identified by the value 0b0111. FEAT_PMUv3p8 implements the functionality identified by the value 0b1000. FEAT_PMUv3p9 implements the functionality identified by the value 0b1001. From Armv8.1, if FEAT_PMUv3 is implemented, the value 0b0001 is not permitted. From Armv8.4, if FEAT_PMUv3 is implemented, the value 0b0100 is not permitted. From Armv8.5, if FEAT_PMUv3 is implemented, the value 0b0101 is not permitted. From Armv8.7, if FEAT_PMUv3 is implemented, the value 0b0110 is not permitted. From Armv8.8, if FEAT_PMUv3 is implemented, the value 0b0111 is not permitted. From Armv8.9, if FEAT_PMUv3 is implemented, the value 0b1000 is not permitted. 0b0000 Performance Monitors Extension not implemented. 0b0001 Performance Monitors Extension, PMUv3 implemented. 0b0100 PMUv3 for Armv8.1. As 0b0001, and adds support for: Extended 16-bit PMEVTYPER<n>_EL0.evtCount field. If EL2 is implemented, the MDCR_EL2.HPMD control. 0b0101 PMUv3 for Armv8.4. As 0b0100, and adds support for the PMMIR_EL1 register. 0b0110 PMUv3 for Armv8.5. As 0b0101, and adds support for: 64-bit event counters. If EL2 is implemented, the MDCR_EL2.HCCD control. If EL3 is implemented, the MDCR_EL3.SCCD control. 0b0111 PMUv3 for Armv8.7. As 0b0110, and adds support for: The PMCR_EL0.FZO and, if EL2 is implemented, MDCR_EL2.HPMFZO controls. If EL3 is implemented, the MDCR_EL3.{MPMX,MCCD} controls. 0b1000 PMUv3 for Armv8.8. As 0b0111, and: Extends the Common event number space to include 0x0040 to 0x00BF and 0x4040 to 0x40BF. Removes the CONSTRAINED UNPREDICTABLE behaviors if a reserved or unimplemented PMU event number is selected. 0b1001 PMUv3 for Armv8.9. As 0b1000, and: Updates the definitions of existing PMU events. Adds support for the PMUSERENR_EL0.UEN control and the PMUACR_EL1 register. Adds support for the EDECR.PME control. 0b1111 IMPLEMENTATION DEFINED form of performance monitors supported, PMUv3 not supported. Arm does not recommend this value for new implementations. RO TraceVer 7 4 7:4 Trace support. Indicates whether System register interface to a trace unit is implemented. All other values are reserved. When trace unit System registers are implemented, see TRCIDR1 for tracing capabilities of the trace unit. 0b0000 Trace unit System registers not implemented. 0b0001 Trace unit System registers implemented. RO DebugVer 3 0 3:0 Debug architecture version. Indicates presence of Armv8 debug architecture. All other values are reserved. FEAT_Debugv8p1 implements the functionality identified by the value 0b0111. FEAT_Debugv8p2 implements the functionality identified by the value 0b1000. FEAT_Debugv8p4 implements the functionality identified by the value 0b1001. FEAT_Debugv8p8 implements the functionality identified by the value 0b1010. FEAT_Debugv8p9 implements the functionality identified by the value 0b1011. From Armv8.1, when FEAT_Debugv8p1 is implemented the value 0b0110 is not permitted. From Armv8.2, the values 0b0110 and 0b0111 are not permitted. From Armv8.4, the value 0b1000 is not permitted. From Armv8.8, the value 0b1001 is not permitted. From Armv8.9, the value 0b1010 is not permitted. 0b0110 Armv8.0 debug architecture. 0b0111 Armv8.1 debug architecture, FEAT_Debugv8p1. 0b1000 Armv8.2 debug architecture, FEAT_Debugv8p2. 0b1001 Armv8.4 debug architecture, FEAT_Debugv8p4. 0b1010 Armv8.8 debug architecture, FEAT_Debugv8p8. 0b1011 Armv8.9 debug architecture, FEAT_Debugv8p9. RO MRS <Xt>, ID_AA64DFR0_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64DFR0_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64DFR0_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_AA64DFR0_EL1(); end; 2026-03-26 20:27:25 2026-03_rel