ID_AA64DFR1_EL1 AArch64 Debug Feature Register 1 when FEAT_AA64 is implemented Provides top-level information about the debug system in AArch64. Identification Registers ID_AA64DFR1_EL1 is a 64-bit register. ABL_CMPs 63 56 7:0 Number of breakpoints that support address linking, minus 1. All other values are reserved. The number of breakpoints that support address linking is never more than either the number of breakpoints or the number of watchpoints. 0x00..0x3F Number of breakpoints that support address linking minus 1. RO When FEAT_ABLE is implemented 63 56 63:56 Reserved, RES0. Otherwise DPFZS 55 52 55:52 Behavior of the cycle counter when event counting is frozen by a Statistical Profiling management event. FEAT_SPE_DPFZS implements the functionality identified by the value 0b0001. 0b0000 The cycle counter PMCCNTR_EL0 is never affected by PMCR_EL0.FZS. 0b0001 The cycle counter PMCCNTR_EL0 does not count when PMCR_EL0.DP is 1 and counting by event counters accessible to EL1 is frozen by the PMCR_EL0.FZS mechanism. RO EBEP 51 48 51:48 Exception-based event profiling. All other values are reserved. FEAT_EBEP implements the functionality identified by the value 0b0001. 0b0000 Exception-based event profiling not implemented. 0b0001 Exception-based event profiling implemented. RO ITE 47 44 47:44 Instrumentation Trace Extension. All other values are reserved. FEAT_ITE implements the functionality identified by the value 0b0001. 0b0000 Instrumentation Trace Extension not implemented. 0b0001 Instrumentation Trace Extension implemented. RO ABLE 43 40 43:40 Address Breakpoint Linking Extension. All other values are reserved. FEAT_BWE implements the address range breakpoints and mismatch breakpoints part of the functionality identified by the value 0b0001. FEAT_ABLE implements the functionality identified by the value 0b0001. 0b0000 Address Breakpoint Linking Extension not implemented. 0b0001 Address Breakpoint Linking Extension implemented. RO PMICNTR 39 36 39:36 PMU fixed-function instruction counter. All other values are reserved. FEAT_PMUv3_ICNTR implements the functionality identified by the value 0b0001. If FEAT_PMUv3 is not implemented, then the only permitted value is 0b0000. 0b0000 PMU fixed-function instruction counter not implemented. 0b0001 PMU fixed-function instruction counter implemented. RO SPMU 35 32 35:32 System PMU extension. All other values are reserved. FEAT_SPMU implements the functionality identified by the value 0b0001. FEAT_SPMU2 implements the functionality identified by the value 0b0010. From Armv9.5, the value 0b0001 is not permitted. 0b0000 System PMU extension not implemented. 0b0001 System PMU extension implemented. 0b0010 As 0b0001, and adds support for SPMZR_EL0. RO CTX_CMPs 31 24 31:24 Context-aware breakpoints. All other values are reserved. If 16 or fewer context-aware breakpoints are implemented, then the value of this field is either 0x00 or the same as ID_AA64DFR0_EL1.CTX_CMPs. If more than 16 context-aware breakpoints are implemented, then the value 0x00 is not permitted. Values greater than ID_AA64DFR1_EL1.BRPs are not permitted. 0x00 ID_AA64DFR0_EL1.CTX_CMPs is the number of context-aware breakpoints, minus 1. 0x01..0x3F Number of context-aware breakpoints minus 1. RO WRPs 23 16 23:16 Watchpoints. All other values are reserved. 0x00 ID_AA64DFR0_EL1.WRPs is the number of watchpoints, minus 1. 0x01..0x3F Number of watchpoints minus 1. RO BRPs 15 8 15:8 Breakpoints. All other values are reserved. If more than 16 breakpoints are implemented, or the index of the highest numbered context-aware breakpoint is not the number of breakpoints minus 1, then the value 0x00 is not permitted. Nonzero values less than ID_AA64DFR0_EL1.BRPs are not permitted. 0x00 ID_AA64DFR0_EL1.BRPs is the number of breakpoints, minus 1. 0x01..0x3F Number of breakpoints minus 1. RO SYSPMUID 7 0 7:0 System PMU ID. Indicates the largest value that can be written to SPMSELR_EL0.SYSPMUSEL. All other values are reserved. Since System PMUs might not be contiguously accessible, this field does not necessarily indicate the total number of accessible System PMUs. 0x00..0x1F The largest supported value that can be written to SPMSELR_EL0.SYSPMUSEL. RO When FEAT_SPMU is implemented 7 0 7:0 Reserved, RES0. Otherwise MRS <Xt>, ID_AA64DFR1_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64DFR1_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64DFR1_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_AA64DFR1_EL1(); end; 2026-03-26 20:27:25 2026-03_rel