ID_AA64ISAR0_EL1 AArch64 Instruction Set Attribute Register 0 when FEAT_AA64 is implemented Provides information about the instructions implemented in AArch64 state. For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'. Identification Registers ID_AA64ISAR0_EL1 is a 64-bit register. RNDR 63 60 63:60 Indicates support for Random Number instructions in AArch64 state. When FEAT_RNG_TRAP is implemented, the value returned by a direct read of ID_AA64ISAR0_EL1.RNDR is further controlled by the value of SCR_EL3.TRNDR. All other values are reserved. FEAT_RNG implements the functionality identified by the value 0b0001. 0b0000 No Random Number instructions are implemented. 0b0001 RNDR and RNDRRS registers are implemented. RO TLB 59 56 59:56 Indicates support for Outer Shareable and TLB range maintenance instructions. All other values are reserved. FEAT_TLBIOS implements the functionality identified by the values 0b0001 and 0b0010. FEAT_TLBIRANGE implements the functionality identified by the value 0b0010. From Armv8.4, the values 0b0000 and 0b0001 are not permitted. 0b0000 Outer Shareable and TLB range maintenance instructions are not implemented. 0b0001 Outer Shareable TLB maintenance instructions are implemented. 0b0010 Outer Shareable and TLB range maintenance instructions are implemented. RO TS 55 52 55:52 Indicates support for flag manipulation instructions. All other values are reserved. FEAT_FlagM implements the functionality identified by the value 0b0001. FEAT_FlagM2 implements the functionality identified by the value 0b0010. In Armv8.4, the value 0b0000 is not permitted. From Armv8.5, the value 0b0001 is not permitted. 0b0000 No flag manipulation instructions are implemented. 0b0001 CFINV, RMIF, SETF16, and SETF8 instructions are implemented. 0b0010 CFINV, RMIF, SETF16, SETF8, AXFLAG, and XAFLAG instructions are implemented. RO FHM 51 48 51:48 Indicates support for the Advanced SIMD half-precision to single-precision multiply instructions. All other values are reserved. FEAT_FHM implements the functionality identified by the value 0b0001. From Armv8.4, if FEAT_FP16 is implemented, the value 0b0000 is not permitted. 0b0000 The Advanced SIMD half-precision to single-precision multiply instructions are not implemented. 0b0001 FMLAL and FMLSL instructions are implemented. RO DP 47 44 47:44 Indicates support for Dot Product instructions in AArch64 state. All other values are reserved. FEAT_DotProd implements the functionality identified by the value 0b0001. From Armv8.4, if FEAT_AdvSIMD is implemented, the value 0b0000 is not permitted. 0b0000 No Dot Product instructions implemented. 0b0001 UDOT and SDOT instructions implemented. RO SM4 43 40 43:40 Indicates support for SM4 instructions in AArch64 state. All other values are reserved. If FEAT_SM4 is not implemented, the value 0b0001 is reserved. FEAT_SM4 implements the functionality identified by the value 0b0001. This field must have the same value as ID_AA64ISAR0_EL1.SM3. 0b0000 No SM4 instructions implemented. 0b0001 SM4E and SM4EKEY instructions implemented. RO SM3 39 36 39:36 Indicates support for the following SM3 instructions SM3SS1, SM3TT1A, SM3TT1B, SM3TT2A, SM3TT2B, SM3PARTW1, and SM3PARTW2 in AArch64 state. All other values are reserved. If FEAT_SM3 is not implemented, the value 0b0001 is reserved. FEAT_SM3 implements the functionality identified by the value 0b0001. This field must have the same value as ID_AA64ISAR0_EL1.SM4. 0b0000 The specified instructions are not implemented. 0b0001 The specified instructions are implemented. RO SHA3 35 32 35:32 Indicates support for the following SHA3 instructions EOR3, RAX1, XAR, and BCAX in AArch64 state. All other values are reserved. If FEAT_SHA3 is not implemented, the value 0b0001 is reserved. FEAT_SHA3 implements the functionality identified by the value 0b0001. If the value of ID_AA64ISAR0_EL1.SHA1 is 0b0000, this field must have the value 0b0000. If the value of this field is 0b0001, ID_AA64ISAR0_EL1.SHA2 must have the value 0b0010. 0b0000 The specified instructions are not implemented. 0b0001 The specified instructions are implemented. RO RDM 31 28 31:28 Indicates support for SQRDMLAH and SQRDMLSH instructions in AArch64 state. All other values are reserved. FEAT_RDM implements the functionality identified by the value 0b0001. From Armv8.1, the value 0b0000 is not permitted. 0b0000 No RDMA instructions implemented. 0b0001 SQRDMLAH and SQRDMLSH instructions implemented. RO 27 24 27:24 Reserved, RES0. Atomic 23 20 23:20 Indicates support for Atomic instructions in AArch64 state. All other values are reserved. FEAT_LSE implements the functionality identified by the value 0b0010. FEAT_LSE128 implements the functionality identified by the value 0b0011. From Armv8.1, the value 0b0000 is not permitted. 0b0000 No Atomic instructions implemented. 0b0010 LDADD, LDCLR, LDEOR, LDSET, LDSMAX, LDSMIN, LDUMAX, LDUMIN, CAS, CASP, and SWP instructions implemented. 0b0011 As for 0b0010, plus 128-bit instructions LDCLRP, LDSETP, and SWPP. RO CRC32 19 16 19:16 Indicates support for the following CRC32 instructions CRC32B, CRC32H, CRC32W, CRC32X, CRC32CB, CRC32CH, CRC32CW, and CRC32CX in AArch64 state. All other values are reserved. FEAT_CRC32 implements the functionality identified by the value 0b0001. From Armv8.1, the value 0b0000 is not permitted. 0b0000 The specified instructions are not implemented. 0b0001 The specified instructions are implemented. RO SHA2 15 12 15:12 Indicates support for SHA2 instructions in AArch64 state. All other values are reserved. FEAT_SHA256 implements the functionality identified by the value 0b0001. FEAT_SHA512 implements the functionality identified by the value 0b0010. If the value of ID_AA64ISAR0_EL1.SHA1 is 0b0000, this field must have the value 0b0000. If the value of this field is 0b0010, ID_AA64ISAR0_EL1.SHA3 must have the value 0b0001. 0b0000 No SHA2 instructions implemented. 0b0001 Implements instructions: SHA256H, SHA256H2, SHA256SU0, and SHA256SU1. 0b0010 Implements instructions: SHA256H, SHA256H2, SHA256SU0, and SHA256SU1. SHA512H, SHA512H2, SHA512SU0, and SHA512SU1. RO SHA1 11 8 11:8 Indicates support for the following SHA1 instructions SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 in AArch64 state. All other values are reserved. FEAT_SHA1 implements the functionality identified by the value 0b0001. If the value of ID_AA64ISAR0_EL1.SHA2 is 0b0000, this field must have the value 0b0000. 0b0000 The specified instructions are not implemented. 0b0001 The specified instructions are implemented. RO AES 7 4 7:4 Indicates support for AES instructions in AArch64 state. FEAT_AES implements the functionality identified by the value 0b0001. FEAT_PMULL implements the functionality identified by the value 0b0010. All other values are reserved. 0b0000 No AES instructions implemented. 0b0001 AESE, AESD, AESMC, and AESIMC instructions implemented. 0b0010 As for 0b0001, plus PMULL and PMULL2 instructions operating on 64-bit source elements. RO 3 0 3:0 Reserved, RES0. MRS <Xt>, ID_AA64ISAR0_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64ISAR0_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64ISAR0_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_AA64ISAR0_EL1(); end; 2026-03-26 20:27:25 2026-03_rel