ID_AA64ISAR1_EL1 AArch64 Instruction Set Attribute Register 1 when FEAT_AA64 is implemented Provides information about the features and instructions implemented in AArch64 state. For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'. Identification Registers ID_AA64ISAR1_EL1 is a 64-bit register. LS64 63 60 63:60 Indicates support for LD64B and ST64B* instructions, and the ACCDATA_EL1 register. All other values are reserved. FEAT_LS64 implements the functionality identified by 0b0001. FEAT_LS64_V implements the functionality identified by 0b0010. FEAT_LS64_ACCDATA implements the functionality identified by 0b0011. FEAT_LS64WB implements the functionality identified by 0b0100. 0b0000 No LD64B or ST64B instructions are supported. 0b0001 The LD64B and ST64B instructions are supported. 0b0010 As 0b0001, and adds the ST64BV instruction and traps. 0b0011 As 0b0010, and adds the ST64BV0 instruction, ACCDATA_EL1 register, and traps. 0b0100 As 0b0011, and adds support for atomic accesses to Write-back Cacheable, Shareable memory using one of the following: LD64B and ST64B instructions. SIMD&FP instructions that load or store a pair of 128-bit registers by generating 32-byte single-copy atomic accesses. RO XS 59 56 59:56 Indicates support for the XS attribute, the TLBI and DSB instructions with the nXS qualifier, and the HCRX_EL2.{FGTnXS, FnXS} fields in AArch64 state. All other values are reserved. FEAT_XS implements the functionality identified by 0b0001. From Armv8.7, the value 0b0000 is not permitted. 0b0000 The XS attribute, the TLBI and DSB instructions with the nXS qualifier, and the HCRX_EL2.{FGTnXS, FnXS} fields are not supported. 0b0001 The XS attribute, the TLBI and DSB instructions with the nXS qualifier, and the HCRX_EL2.{FGTnXS, FnXS} fields are supported. RO I8MM 55 52 55:52 Indicates support for the following Advanced SIMD Int8 matrix multiplication instructions SMMLA, SUDOT, UMMLA, USMMLA, and USDOT in AArch64 state. All other values are reserved. FEAT_I8MM implements the functionality identified by 0b0001. When Advanced SIMD and SVE are both implemented, this field must return the same value as ID_AA64ZFR0_EL1.I8MM. From Armv8.6, the value 0b0000 is not permitted. 0b0000 The specified instructions are not implemented. 0b0001 The specified instructions are implemented. RO DGH 51 48 51:48 Indicates support for the Data Gathering Hint instruction. All other values are reserved. FEAT_DGH implements the functionality identified by 0b0001. From Armv8.0, the permitted values are 0b0000 and 0b0001. If the DGH instruction has no effect in preventing the merging of memory accesses, the value of this field is 0b0000. 0b0000 Data Gathering Hint is not implemented. 0b0001 Data Gathering Hint is implemented. RO BF16 47 44 47:44 Indicates support for Advanced SIMD and floating-point BFloat16 instructions in AArch64 state. All other values are reserved. FEAT_BF16 implements the functionality identified by 0b0001. FEAT_EBF16 implements the functionality identified by 0b0010. When FEAT_SVE or FEAT_SME is implemented, this field must return the same value as ID_AA64ZFR0_EL1.BF16. From Armv8.6 and Armv9.1, the value 0b0000 is not permitted. 0b0000 BFloat16 instructions are not implemented. 0b0001 BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT, and BFMMLA instructions are implemented. 0b0010 As 0b0001, but the FPCR.EBF field is also supported. RO SPECRES 43 40 43:40 Indicates support for prediction invalidation instructions in AArch64 state. All other values are reserved. FEAT_SPECRES implements the functionality identified by 0b0001. FEAT_SPECRES2 implements the functionality identified by 0b0010. From Armv8.5, the value 0b0000 is not permitted. From Armv8.9, the value 0b0001 is not permitted. 0b0000 Prediction invalidation instructions are not implemented. 0b0001 CFP RCTX, DVP RCTX and CPP RCTX instructions are implemented. 0b0010 As 0b0001, and COSP RCTX instruction is implemented. RO SB 39 36 39:36 Indicates support for SB instruction in AArch64 state. All other values are reserved. FEAT_SB implements the functionality identified by 0b0001. From Armv8.5, the value 0b0000 is not permitted. 0b0000 SB instruction is not implemented. 0b0001 SB instruction is implemented. RO FRINTTS 35 32 35:32 Indicates support for FRINT32Z, FRINT32X, FRINT64Z, and FRINT64X instructions. All other values are reserved. FEAT_FRINTTS implements the functionality identified by 0b0001. From Armv8.5, the value 0b0000 is not permitted. 0b0000 The specified instructions are not implemented. 0b0001 The specified instructions are implemented. RO GPI 31 28 31:28 Indicates support for an IMPLEMENTATION DEFINED algorithm is implemented in the PE for generic code authentication in AArch64 state. All other values are reserved. When this field is nonzero, FEAT_PACIMP is implemented. From Armv8.3, the permitted values are 0b0000 and 0b0001. If the value of ID_AA64ISAR1_EL1.GPA is nonzero, or the value of ID_AA64ISAR2_EL1.GPA3 is nonzero, this field must have the value 0b0000. 0b0000 Generic Authentication using an IMPLEMENTATION DEFINED algorithm is not implemented. 0b0001 Generic Authentication using an IMPLEMENTATION DEFINED algorithm is implemented. This includes the PACGA instruction. RO GPA 27 24 27:24 Indicates whether the QARMA5 algorithm is implemented in the PE for generic code authentication in AArch64 state. All other values are reserved. FEAT_PACQARMA5 implements the functionality identified by 0b0001. When this field is nonzero, FEAT_PACQARMA5 is implemented. From Armv8.3, the permitted values are 0b0000 and 0b0001. If the value of ID_AA64ISAR1_EL1.GPI is nonzero, or the value of ID_AA64ISAR2_EL1.GPA3 is nonzero, this field must have the value 0b0000. 0b0000 Generic Authentication using the QARMA5 algorithm is not implemented. 0b0001 Generic Authentication using the QARMA5 algorithm is implemented. This includes the PACGA instruction. RO LRCPC 23 20 23:20 Indicates support for weaker release consistency, RCpc, based model. All other values are reserved. FEAT_LRCPC implements the functionality identified by the value 0b0001. FEAT_LRCPC2 implements the functionality identified by the value 0b0010. FEAT_LRCPC3 implements the functionality identified by the value 0b0011. From Armv8.3, the value 0b0000 is not permitted. From Armv8.4, the value 0b0001 is not permitted. 0b0000 RCpc instructions are not implemented. 0b0001 The no offset LDAPR, LDAPRB, and LDAPRH instructions are implemented. 0b0010 As 0b0001, and the LDAPUR (unscaled), LDAPURB (unscaled), LDAPURSB (unscaled), LDAPURH (unscaled), LDAPURSH (unscaled), LDAPURSW (unscaled), STLUR (unscaled), STLURB (unscaled) and STLURH (unscaled) instructions are implemented. 0b0011 As 0b0010, and the post-index LDAPR, LDIAPP, STILP, and pre-index STLR instructions are implemented. If Advanced SIMD and floating-point is implemented, then the LDAPUR (SIMD&FP), LDAP1 (SIMD&FP), STLUR (SIMD&FP), and STL1 (SIMD&FP) instructions are implemented in Advanced SIMD and floating-point. RO FCMA 19 16 19:16 Indicates support for complex number addition and multiplication, where numbers are stored in vectors. All other values are reserved. FEAT_FCMA implements the functionality identified by the value 0b0001. From Armv8.3, if Advanced SIMD or floating-point is implemented, the value 0b0000 is not permitted. From Armv8.3, if Advanced SIMD or floating-point is not implemented, the only permitted value is 0b0000. 0b0000 The FCMLA and FCADD instructions are not implemented. 0b0001 The FCMLA and FCADD instructions are implemented. RO JSCVT 15 12 15:12 Indicates support for JavaScript conversion from double-precision floating-point values to integers in AArch64 state. All other values are reserved. FEAT_JSCVT implements the functionality identified by 0b0001. From Armv8.3, if Advanced SIMD or floating-point is implemented, the value 0b0000 is not permitted. From Armv8.3, if Advanced SIMD or floating-point is not implemented, the only permitted value is 0b0000. 0b0000 The FJCVTZS instruction is not implemented. 0b0001 The FJCVTZS instruction is implemented. RO API 11 8 11:8 Indicates whether an IMPLEMENTATION DEFINED algorithm is implemented in the PE for address authentication, in AArch64 state. This applies to all Pointer Authentication instructions other than the PACGA instruction. All other values are reserved. FEAT_PAuth implements the functionality identified by 0b0001. FEAT_EPAC implements the functionality identified by 0b0010. FEAT_PAuth2 implements the functionality identified by 0b0011. FEAT_FPAC implements the functionality identified by 0b0100. FEAT_FPACCOMBINE implements the functionality identified by 0b0101. FEAT_PAuth_LR implements the functionality identified by 0b0110. When this field is nonzero, FEAT_PACIMP is implemented. In Armv8.3, the permitted values are 0b0000, 0b0001, 0b0010, 0b0011, 0b0100, and 0b0101. From Armv8.6, the permitted values are 0b0000, 0b0011, 0b0100, and 0b0101. From Armv9.5, the permitted values are 0b0000, 0b0011, 0b0100, 0b0101, and 0b0110. If the value of ID_AA64ISAR1_EL1.APA is nonzero, or the value of ID_AA64ISAR2_EL1.APA3 is nonzero, this field must have the value 0b0000. 0b0000 Address Authentication using an IMPLEMENTATION DEFINED algorithm is not implemented. 0b0001 Address Authentication using an IMPLEMENTATION DEFINED algorithm is implemented, FEAT_EPAC and FEAT_PAuth2 are not implemented. 0b0010 Address Authentication using an IMPLEMENTATION DEFINED algorithm is implemented, FEAT_EPAC is implemented, and FEAT_PAuth2 is not implemented. 0b0011 Address Authentication using an IMPLEMENTATION DEFINED algorithm is implemented, FEAT_EPAC is not implemented, and FEAT_PAuth2 is implemented. 0b0100 Address Authentication using an IMPLEMENTATION DEFINED algorithm is implemented, FEAT_EPAC is not implemented, FEAT_PAuth2 and FEAT_FPAC are implemented. 0b0101 Address Authentication using an IMPLEMENTATION DEFINED algorithm is implemented, FEAT_EPAC is not implemented, FEAT_PAuth2, FEAT_FPAC, and FEAT_FPACCOMBINE are implemented. 0b0110 Address Authentication using an IMPLEMENTATION DEFINED algorithm is implemented, including instructions that allow signing of LR using SP and PC as diversifiers, FEAT_EPAC is not implemented, FEAT_PAuth2, FEAT_FPAC, FEAT_FPACCOMBINE, and FEAT_PAuth_LR are implemented. RO APA 7 4 7:4 Indicates whether the QARMA5 algorithm is implemented in the PE for address authentication, in AArch64 state. This applies to all Pointer Authentication instructions other than the PACGA instruction. All other values are reserved. FEAT_PAuth implements the functionality identified by 0b0001. FEAT_EPAC implements the functionality identified by 0b0010. FEAT_PAuth2 implements the functionality identified by 0b0011. FEAT_FPAC implements the functionality identified by 0b0100. FEAT_FPACCOMBINE implements the functionality identified by 0b0101. FEAT_PAuth_LR implements the functionality identified by 0b0110. When this field is nonzero, FEAT_PACQARMA5 is implemented. In Armv8.3, the permitted values are 0b0000, 0b0001, 0b0010, 0b0011, 0b0100, and 0b0101. From Armv8.6, the permitted values are 0b0000, 0b0011, 0b0100, and 0b0101. From Armv9.5, the permitted values are 0b0000, 0b0011, 0b0100, 0b0101, and 0b0110. If the value of ID_AA64ISAR1_EL1.API is nonzero, or the value of ID_AA64ISAR2_EL1.APA3 is nonzero, this field must have the value 0b0000. 0b0000 Address Authentication using the QARMA5 algorithm is not implemented. 0b0001 Address Authentication using the QARMA5 algorithm is implemented, FEAT_EPAC and FEAT_PAuth2 are not implemented. 0b0010 Address Authentication using the QARMA5 algorithm is implemented, FEAT_EPAC is implemented, and FEAT_PAuth2 is not implemented. 0b0011 Address Authentication using the QARMA5 algorithm is implemented, FEAT_EPAC is not implemented, and FEAT_PAuth2 is implemented. 0b0100 Address Authentication using the QARMA5 algorithm is implemented, FEAT_EPAC is not implemented, FEAT_PAuth2 and FEAT_FPAC are implemented. 0b0101 Address Authentication using the QARMA5 algorithm is implemented, FEAT_EPAC is not implemented, FEAT_PAuth2, FEAT_FPAC, and FEAT_FPACCOMBINE are implemented. 0b0110 Address Authentication using the QARMA5 algorithm is implemented, including instructions that allow signing of LR using SP and PC as diversifiers, FEAT_EPAC is not implemented, FEAT_PAuth2, FEAT_FPAC, FEAT_FPACCOMBINE, and FEAT_PAuth_LR are implemented. RO DPB 3 0 3:0 Data Persistence writeback. Indicates support for the DC CVAP and DC CVADP instructions in AArch64 state. All other values are reserved. FEAT_DPB implements the functionality identified by the value 0b0001. FEAT_DPB2 implements the functionality identified by the value 0b0010. From Armv8.2, the value 0b0000 is not permitted. From Armv8.5, the value 0b0001 is not permitted. 0b0000 DC CVAP not supported. 0b0001 DC CVAP supported. 0b0010 DC CVAP and DC CVADP supported. RO MRS <Xt>, ID_AA64ISAR1_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64ISAR1_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64ISAR1_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_AA64ISAR1_EL1(); end; 2026-03-26 20:27:25 2026-03_rel