ID_AA64ISAR2_EL1 AArch64 Instruction Set Attribute Register 2 when FEAT_AA64 is implemented Provides information about the features and instructions implemented in AArch64 state. For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'. Identification Registers Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3. ID_AA64ISAR2_EL1 is a 64-bit register. ATS1A 63 60 63:60 Indicates support for address translation instructions, which perform stage 1 address translation for the given virtual address without checking for stage 1 permissions. All other values are reserved. 0b0000 Address Translate Stage 1 instructions without Permissions Checks are not implemented 0b0001 Address Translate Stage 1 instructions without Permissions Checks are implemented. RO LUT 59 56 59:56 Indicates support for: Advanced SIMD lookup table instructions with 2-bit and 4-bit indices. If FEAT_SVE2 or FEAT_SME2 is implemented, SVE lookup table instructions with 2-bit and 4-bit indices. All other values are reserved. FEAT_LUT implements the functionality identified by the value 0b0001. From Armv9.5, if FEAT_AdvSIMD is implemented, the value 0b0000 is not permitted. 0b0000 The specified instructions are not implemented. 0b0001 Lookup table instructions with 2-bit indices LUTI2 and 4-bit indices LUTI4 are implemented. RO CSSC 55 52 55:52 Indicates support for common short sequence compression instructions. If FEAT_CMPBR is implemented, indicates support for compare and branch instructions. All other values are reserved. FEAT_CSSC implements the functionality identified by the value 0b0001. FEAT_CMPBR implements the functionality identified by the value 0b0010. From Armv9.4, the value 0b0000 is not permitted. From Armv9.6, the value 0b0001 is not permitted. 0b0000 Common short sequence compression instructions are not implemented. 0b0001 The following common short sequence compression instructions are implemented: 32-bit and 64-bit ABS, CNT, CTZ 32-bit SMAX, UMAX, SMIN, UMIN (immediate). 64-bit SMAX, UMAX, SMIN, UMIN (immediate). 32-bit SMAX, UMAX, SMIN, UMIN (register). 64-bit SMAX, UMAX, SMIN, UMIN (register). 0b0010 As 0b0001, and adds compare and branch instructions: CBB<cc>. CB<cc> (immediate), CB<cc> (register). CBH<cc>. RO RPRFM 51 48 51:48 RPRFM hint instruction. All other values are reserved. FEAT_RPRFM implements the functionality identified by the value 0b0001. 0b0000 RPRFM hint instruction is not implemented and is treated as a NOP. 0b0001 RPRFM hint instruction is implemented. RO PCDPHINT 47 44 47:44 Indicates support for producer-consumer data placement hints. FEAT_PCDPHINT implements the functionality identified by the value 0b0001. 0b0000 The STSHH and PRFM IR hint instructions are not implemented. 0b0001 The STSHH and PRFM IR hint instructions are implemented. RO PRFMSLC 43 40 43:40 Indicates whether the PRFM and PRFUM instructions support a system level cache option. All other values are reserved. FEAT_PRFMSLC implements the functionality identified by the value 0b0001. 0b0000 The PRFM and PRFUM instructions do not support the SLC target. 0b0001 The PRFM and PRFUM instructions support the SLC target. RO SYSINSTR_128 39 36 39:36 SYSINSTR_128. Indicates support for System instructions that can take 128-bit inputs. All other values are reserved. FEAT_SYSINSTR128 implements the functionality identified by the value 0b0001. 0b0000 System instructions that can take 128-bit inputs are not supported. 0b0001 System instructions that can take 128-bit inputs are supported. RO SYSREG_128 35 32 35:32 SYSREG_128. Indicates support for instructions to access 128-bit System Registers. All other values are reserved. FEAT_SYSREG128 implements the functionality identified by the value 0b0001. 0b0000 Instructions to access 128-bit System Registers are not supported. 0b0001 Instructions to access 128-bit System Registers are supported. RO CLRBHB 31 28 31:28 Indicates support for the CLRBHB instruction in AArch64 state. All other values are reserved. FEAT_CLRBHB implements the functionality identified by the value 0b0001. From Armv8.9, the value 0b0000 is not permitted. 0b0000 CLRBHB instruction is not implemented. 0b0001 CLRBHB instruction is implemented. RO PAC_frac 27 24 27:24 Indicates which address bit is used to determine the size of the PAC field. All other values are reserved. FEAT_CONSTPACFIELD implements the functionality identified by the value 0b0001. From Armv8.3, the permitted values are 0b0000 and 0b0001. 0b0000 The address bit which is used to define the size of the PAC field is dependent on whether address tagging is used. 0b0001 The address bit which is used to define the size of the PAC field is fixed. RO BC 23 20 23:20 Indicates support for the BC instruction in AArch64 state. All other values are reserved. FEAT_HBC implements the functionality identified by the value 0b0001. From Armv8.8, the value 0b0000 is not permitted. 0b0000 BC instruction is not implemented. 0b0001 BC instruction is implemented. RO MOPS 19 16 19:16 Indicates support for the Memory Copy and Memory Set instructions in AArch64 state. All other values are reserved. FEAT_MOPS implements the functionality identified by the value 0b0001. From Armv8.8, the value 0b0000 is not permitted. 0b0000 The Memory Copy and Memory Set instructions are not implemented in AArch64 state. 0b0001 The Memory Copy and Memory Set instructions are implemented in AArch64 state with the following exception. If FEAT_MTE is implemented, then SETGP*, SETGM* and SETGE* instructions are also supported. RO APA3 15 12 15:12 Indicates whether the QARMA3 algorithm is implemented in the PE for address authentication in AArch64 state. This applies to all Pointer Authentication instructions other than the PACGA instruction. All other values are reserved. FEAT_PAuth implements the functionality identified by the value 0b0001. FEAT_EPAC implements the functionality identified by the value 0b0010. FEAT_PAuth2 implements the functionality identified by the value 0b0011. FEAT_FPAC implements the functionality identified by the value 0b0100. FEAT_FPACCOMBINE implements the functionality identified by the value 0b0101. FEAT_PAuth_LR implements the functionality identified by the value 0b0110. When this field is nonzero, FEAT_PACQARMA3 is implemented. In Armv8.3, the permitted values are 0b0000, 0b0001, 0b0010, 0b0011, 0b0100, and 0b0101. From Armv8.6, the permitted values are 0b0000, 0b0011, 0b0100, and 0b0101. From Armv9.5, the permitted values are 0b0000, 0b0011, 0b0100, 0b0101, and 0b0110. If the value of ID_AA64ISAR1_EL1.API is nonzero, or the value of ID_AA64ISAR1_EL1.APA is nonzero, this field must have the value 0b0000. 0b0000 Address Authentication using the QARMA3 algorithm is not implemented. 0b0001 Address Authentication using the QARMA3 algorithm is implemented, FEAT_EPAC and FEAT_PAuth2 are not implemented. 0b0010 Address Authentication using the QARMA3 algorithm is implemented, FEAT_EPAC is implemented, and FEAT_PAuth2 is not implemented. 0b0011 Address Authentication using the QARMA3 algorithm is implemented, FEAT_EPAC is not implemented, and FEAT_PAuth2 is implemented. 0b0100 Address Authentication using the QARMA3 algorithm is implemented, FEAT_EPAC is not implemented, FEAT_PAuth2 and FEAT_FPAC are implemented. 0b0101 Address Authentication using the QARMA3 algorithm is implemented, FEAT_EPAC is not implemented, FEAT_PAuth2, FEAT_FPAC, and FEAT_FPACCOMBINE are implemented. 0b0110 Address Authentication using the QARMA3 algorithm is implemented, including instructions that allow signing of LR using SP and PC as diversifiers, FEAT_EPAC is not implemented, FEAT_PAuth2, FEAT_FPAC, FEAT_FPACCOMBINE, and FEAT_PAuth_LR are implemented. RO GPA3 11 8 11:8 Indicates whether the QARMA3 algorithm is implemented in the PE for generic code authentication in AArch64 state. All other values are reserved. FEAT_PACQARMA3 implements the functionality identified by the value 0b0001. When this field is nonzero, FEAT_PACQARMA3 is implemented. From Armv8.3, the permitted values are 0b0000 and 0b0001. If the value of ID_AA64ISAR1_EL1.GPI is nonzero, or the value of ID_AA64ISAR1_EL1.GPA is nonzero, this field must have the value 0b0000. 0b0000 Generic Authentication using the QARMA3 algorithm is not implemented. 0b0001 Generic Authentication using the QARMA3 algorithm is implemented. This includes the PACGA instruction. RO RPRES 7 4 7:4 Indicates support for 12 bits of mantissa in single-precision reciprocal and reciprocal square root instructions in AArch64 state, when FPCR.AH is 1. All other values are reserved. FEAT_RPRES implements the functionality identified by the value 0b0001. When FPCR.AH is 0, the floating-point reciprocal estimate and reciprocal square root estimate instructions give 8 bits of mantissa. 0b0000 Single-precision reciprocal and reciprocal square root estimates give 8 bits of mantissa, when FPCR.AH is 1. 0b0001 Single-precision reciprocal and reciprocal square root estimates give 12 bits of mantissa, when FPCR.AH is 1. RO WFxT 3 0 3:0 Indicates support for the WFET and WFIT instructions in AArch64 state. All other values are reserved. FEAT_WFxT implements the functionality identified by the value 0b0010. From Armv8.7, the only permitted value is 0b0010. 0b0000 WFET and WFIT are not supported. 0b0010 WFET and WFIT are supported, and the register number is reported in the ESR_ELx on exceptions. RO MRS <Xt>, ID_AA64ISAR2_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_AA64ISAR2_EL1()) || ImpDefBool("ID_AA64ISAR2_EL1 trapped by HCR_EL2.TID3")) && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64ISAR2_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64ISAR2_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_AA64ISAR2_EL1(); end; 2026-03-26 20:27:25 2026-03_rel