ID_AA64ISAR3_EL1 AArch64 Instruction Set Attribute Register 3 when FEAT_AA64 is implemented Provides information about the features and instructions implemented in AArch64 state. For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'. Identification Registers Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3. ID_AA64ISAR3_EL1 is a 64-bit register. 63 32 63:32 Reserved, RES0. FPRCVT 31 28 31:28 Indicates support for the following conversion between floating-point and integer instructions with only scalar SIMD&FP register operands and results, and with different input and output register sizes, when the PE is not in Streaming SVE mode: FCVTAS (scalar SIMD&FP), FCVTAU (scalar SIMD&FP). FCVTMS (scalar SIMD&FP), FCVTMU (scalar SIMD&FP). FCVTNS (scalar SIMD&FP), FCVTNU (scalar SIMD&FP). FCVTPS (scalar SIMD&FP), FCVTPU (scalar SIMD&FP). FCVTZS (scalar SIMD&FP), FCVTZU (scalar SIMD&FP). SCVTF (scalar SIMD&FP), UCVTF (scalar SIMD&FP). If FEAT_SME is implemented, indicates support for the above instructions, as well as the following conversion between floating-point and integer instructions with only scalar SIMD&FP register operands and results, and with the same input and output register sizes, when the PE is in Streaming SVE mode: FCVTAS (vector), FCVTAU (vector). FCVTMS (vector), FCVTMU (vector). FCVTNS (vector), FCVTNU (vector). FCVTPS (vector), FCVTPU (vector). FCVTZS (vector), FCVTZU (vector). SCVTF (vector), UCVTF (vector). FEAT_FPRCVT implements the functionality identified by the value 0b0001. From Armv9.6, if FEAT_FP is implemented, the value 0b0000 is not permitted. 0b0000 The specified instructions are not implemented. 0b0001 The specified instructions are implemented. RO LSUI 27 24 27:24 Support for the following load and store unprivileged instructions: LDTXR, STTXR. LDATXR, STLTXR. CAST, CASAT, CASALT, CASLT. CASPT, CASPAT, CASPALT, CASPLT. LDTP, STTP. LDTP (SIMD&FP), STTP (SIMD&FP). LDTNP, STTNP. LDTNP (SIMD&FP), STTNP (SIMD&FP). SWPT, SWPTA, SWPTL, SWPTAL. LDTADD, LDTADDA, LDTADDAL, LDTADDL. LDTSET, LDTSETA, LDTSETAL, LDTSETL. LDTCLR, LDTCLRA, LDTCLRAL, LDTCLRL. STTADD, STTADDL. STTSET, STTSETL. STTCLR, STTCLRL. FEAT_LSUI implements the functionality identified by the value 0b0001. 0b0000 The specified instructions are not implemented. 0b0001 The specified instructions are implemented. RO OCCMO 23 20 23:20 Indicates support for the following cache maintenance operation to the Outer cache level instructions: DC CIVAOC. DC CVAOC. If FEAT_MTE is implemented: DC CIGDVAOC. DC CGDVAOC. FEAT_OCCMO implements the functionality identified by the value 0b0001. From Armv9.6, the value 0b0000 is not permitted. 0b0000 The specified instructions are not implemented. 0b0001 The specified instructions are implemented. RO LSFE 19 16 19:16 Indicates support for the following A64 Base atomic floating-point in-memory instructions: Floating-point atomic add in memory: LDFADD, LDFADDA, LDFADDAL, and LDFADDL. BFloat16 atomic add in memory: LDBFADD, LDBFADDA, LDBFADDAL, and LDBFADDL. Floating-point atomic maximum in memory: LDFMAX, LDFMAXA, LDFMAXAL, and LDFMAXL. BFloat16 atomic maximum in memory: LDBFMAX, LDBFMAXA, LDBFMAXAL, and LDBFMAXL. Floating-point atomic maximum number in memory: LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, and LDFMAXNML. BFloat16 atomic maximum number in memory: LDBFMAXNM, LDBFMAXNMA, LDBFMAXNMAL, and LDBFMAXNML. Floating-point atomic minimum in memory: LDFMIN, LDFMINA, LDFMINAL, and LDFMINL. BFloat16 atomic minimum in memory: LDBFMIN, LDBFMINA, LDBFMINAL, and LDBFMINL. Floating-point atomic minimum number in memory: LDFMINNM, LDFMINNMA, LDFMINNMAL, and LDFMINNML. BFloat16 atomic minimum number in memory: LDBFMINNM, LDBFMINNMA, LDBFMINNMAL, and LDBFMINNML. Floating-point atomic add in memory, without return: STFADD and STFADDL. BFloat16 atomic add in memory, without return: STBFADD and STBFADDL. Floating-point atomic maximum in memory, without return: STFMAX and STFMAXL. BFloat16 atomic maximum in memory, without return: STBFMAX and STBFMAXL. Floating-point atomic maximum number in memory, without return: STFMAXNM and STFMAXNML. BFloat16 atomic maximum number in memory, without return: STBFMAXNM and STBFMAXNML. Floating-point atomic minimum in memory, without return: STFMIN and STFMINL. BFloat16 atomic minimum in memory, without return: STBFMIN and STBFMINL. Floating-point atomic minimum number in memory, without return: STFMINNM and STFMINNML. BFloat16 atomic minimum number in memory, without return: STBFMINNM and STBFMINNML. FEAT_LSFE implements the functionality identified by the value 0b0001 0b0000 Atomic floating-point in-memory instructions are not implemented. 0b0001 The specified Atomic floating-point in-memory instructions are implemented. RO PACM 15 12 15:12 Indicates the implementation of PSTATE.PACM. All other values are reserved. FEAT_PAuth_LR implements the functionality identified by the values 0b0001 and 0b0010. If FEAT_PAuth_LR is implemented, the value 0b0000 is not permitted. If ID_AA64ISAR1_EL1.API is 0b0000, the value 0b0001 is not permitted. If one of FEAT_PACQARMA3 or FEAT_PACQARMA5 are implemented, the value 0b0001 is not permitted. 0b0000 PSTATE.PACM is not implemented. 0b0001 Trivial implementation of PSTATE.PACM. 0b0010 Full implementation of PSTATE.PACM. RO TLBIW 11 8 11:8 Support for TLBI VMALL for Dirty state. All other values are reserved. FEAT_TLBIW implements the functionality identified by the value 0b0001. 0b0000 TLBI VMALL for Dirty state is not supported. 0b0001 TLBI VMALL for Dirty state is supported. RO FAMINMAX 7 4 7:4 Indicates support for the following Advanced SIMD, SVE2, and SME2 instructions that calculate maximum and minimum absolute value: When Advanced SIMD is implemented, the Advanced SIMD instructions FAMAX and FAMIN. When FEAT_SVE2 or FEAT_SME2 is implemented, the SVE2 instructions FAMAX and FAMIN. When FEAT_SME2 is implemented, the SME2 instructions FAMAX (multiple and single vectors), FAMIN (multiple and single vectors), FAMAX (multiple vectors), and FAMIN (multiple vectors). All other values are reserved. FEAT_FAMINMAX implements the functionality identified by the value 0b0001. 0b0000 The specified instructions are not implemented. 0b0001 The specified instructions are implemented. RO CPA 3 0 3:0 Indicates support for Checked Pointer Arithmetic instructions. All other values are reserved. FEAT_CPA implements the functionality identified by the value 0b0001. FEAT_CPA2 implements the functionality identified by the value 0b0010. From Armv9.5, the value 0b0000 is not permitted. 0b0000 Checked Pointer Arithmetic instructions are not implemented. 0b0001 Checked Pointer Arithmetic instructions are implemented. 0b0010 Checked Pointer Arithmetic instructions are implemented, and Checked Pointer Arithmetic can be enabled. RO MRS <Xt>, ID_AA64ISAR3_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_AA64ISAR3_EL1()) || ImpDefBool("ID_AA64ISAR3_EL1 trapped by HCR_EL2.TID3")) && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64ISAR3_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64ISAR3_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_AA64ISAR3_EL1(); end; 2026-03-26 20:27:25 2026-03_rel