ID_AA64MMFR1_EL1 AArch64 Memory Model Feature Register 1 when FEAT_AA64 is implemented Provides information about the implemented memory model and memory management support in AArch64 state. For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'. Identification Registers ID_AA64MMFR1_EL1 is a 64-bit register. ECBHB 63 60 63:60 Indicates support for restrictions on branch history speculation around exceptions. All other values are reserved. FEAT_ECBHB implements the functionality identified by the value 0b0001. From Armv8.9, the value 0b0000 is not permitted. 0b0000 The implementation does not disclose whether restrictions are imposed on branch history speculation around exceptions. 0b0001 The implementation imposes restrictions on branch history speculation around exceptions. RO CMOW 59 56 59:56 Indicates support for cache maintenance instruction permission. All other values are reserved. FEAT_CMOW implements the functionality identified by the value 0b0001. From Armv8.8, the value 0b0000 is not permitted. 0b0000 SCTLR_EL1.CMOW, SCTLR_EL2.CMOW, and HCRX_EL2.CMOW bits are not implemented. 0b0001 SCTLR_EL1.CMOW is implemented. If EL2 is implemented, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are implemented. RO TIDCP1 55 52 55:52 Indicates whether SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP are implemented in AArch64 state. All other values are reserved. FEAT_TIDCP1 implements the functionality identified by the value 0b0001. From Armv8.8, the value 0b0000 is not permitted. 0b0000 SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are not implemented and are RES0. 0b0001 SCTLR_EL1.TIDCP bit is implemented. If EL2 is implemented, SCTLR_EL2.TIDCP bit is implemented. RO nTLBPA 51 48 51:48 Indicates support for intermediate caching of translation table walks. Non-coherent physical translation caches are non-coherent caches of previous valid translation table entries since the last completed relevant TLBI applicable to the PE, where either: The caching is indexed by the physical address of the location holding the translation table entry. The caching is used for stage 1 translations and is indexed by the intermediate physical address of the location holding the translation table entry. All other values are reserved. FEAT_nTLBPA implements the functionality identified by the value 0b0001. 0b0000 The intermediate caching of translation table walks might include non-coherent physical translation caches. 0b0001 The intermediate caching of translation table walks does not include non-coherent physical translation caches. RO AFP 47 44 47:44 Indicates support for FPCR.{AH, FIZ, NEP}. All other values are reserved. FEAT_AFP implements the functionality identified by the value 0b0001. From Armv8.7, if Advanced SIMD and floating-point is implemented, the value 0b0000 is not permitted. 0b0000 The FPCR.{AH, FIZ, NEP} fields are not supported. 0b0001 The FPCR.{AH, FIZ, NEP} fields are supported. RO HCX 43 40 43:40 Indicates support for HCRX_EL2 and its associated EL3 trap. All other values are reserved. FEAT_HCX implements the functionality identified by the value 0b0001. From Armv8.7, if EL2 is implemented, the value 0b0000 is not permitted. 0b0000 HCRX_EL2 and its associated EL3 trap are not supported. 0b0001 HCRX_EL2 and its associated EL3 trap are supported. RO ETS 39 36 39:36 Indicates support for Enhanced Translation Synchronization. All other values are reserved. FEAT_ETS2 implements the functionality identified by the value 0b0010. FEAT_ETS3 implements the functionality identified by the value 0b0011. From Armv8.8, the values 0b0000 and 0b0001 are not permitted. From Armv9.5, the value 0b0010 is not permitted. 0b0000 Enhanced Translation Synchronization is not supported. 0b0001 Enhanced Translation Synchronization is not supported. 0b0010 FEAT_ETS2 is implemented. 0b0011 FEAT_ETS3 is implemented. RO TWED 35 32 35:32 Indicates support for the configurable delayed trapping of WFE and WFET. All other values are reserved. FEAT_TWED implements the functionality identified by the value 0b0001. 0b0000 Configurable delayed trapping of WFE and WFET are not supported. 0b0001 Configurable delayed trapping of WFE and WFET are supported. RO XNX 31 28 31:28 Indicates support for execute-never control distinction by Exception level at stage 2. All other values are reserved. FEAT_XNX implements the functionality identified by the value 0b0001. From Armv8.2, the value 0b0000 is not permitted. 0b0000 Distinction between EL0 and EL1 execute-never control at stage 2 not supported. 0b0001 Distinction between EL0 and EL1 execute-never control at stage 2 supported. RO SpecSEI 27 24 3:0 Describes whether the PE can generate SError exceptions from speculative reads of memory, including speculative instruction fetches. All other values are reserved. FEAT_SpecSEI implements the functionality identified by the value 0b0001. 0b0000 The PE never generates an SError exception due to an External abort on a speculative read. 0b0001 The PE might generate an SError exception due to an External abort on a speculative read. RO When FEAT_RAS is implemented 27 24 27:24 Reserved, RES0. Otherwise PAN 23 20 23:20 Privileged Access Never. Indicates support for the PAN bit in PSTATE, SPSR_EL1, SPSR_EL2, SPSR_EL3, and DSPSR_EL0. All other values are reserved. FEAT_PAN implements the functionality identified by the value 0b0001. FEAT_PAN2 implements the functionality added by the value 0b0010. FEAT_PAN3 implements the functionality added by the value 0b0011. From Armv8.1, the value 0b0000 is not permitted. From Armv8.2, the value 0b0001 is not permitted. From Armv8.7, the value 0b0010 is not permitted. 0b0000 PAN not supported. 0b0001 PAN supported. 0b0010 PAN supported and AT S1E1RP and AT S1E1WP instructions supported. 0b0011 PAN supported, AT S1E1RP and AT S1E1WP instructions supported, and SCTLR_EL1.EPAN and SCTLR_EL2.EPAN bits supported. RO LO 19 16 19:16 LORegions. Indicates support for LORegions. All other values are reserved. FEAT_LOR implements the functionality identified by the value 0b0001. From Armv8.1, the value 0b0000 is not permitted. 0b0000 LORegions not supported. 0b0001 LORegions supported. RO HPDS 15 12 15:12 Hierarchical Permission Disables. Indicates support for disabling hierarchical controls in translation tables. All other values are reserved. FEAT_HPDS implements the functionality identified by the value 0b0001. FEAT_HPDS2 implements the functionality identified by the value 0b0010. From Armv8.1, the value 0b0000 is not permitted. 0b0000 Disabling of hierarchical controls not supported. 0b0001 Disabling of hierarchical controls supported with the TCR_EL1.{HPD1, HPD0}, TCR_EL2.HPD or TCR_EL2.{HPD1, HPD0}, and TCR_EL3.HPD bits. 0b0010 As for value 0b0001, and adds possible hardware allocation of bits[62:59] of the Translation table descriptors from the final lookup level for IMPLEMENTATION DEFINED use. RO VH 11 8 11:8 Virtualization Host Extensions. All other values are reserved. FEAT_VHE implements the functionality identified by the value 0b0001. From Armv8.1, the value 0b0000 is not permitted. 0b0000 Virtualization Host Extensions not supported. 0b0001 Virtualization Host Extensions supported. RO VMIDBits 7 4 7:4 Number of VMID bits. All other values are reserved. FEAT_VMID16 implements the functionality identified by the value 0b0010. 0b0000 8 bits 0b0010 16 bits RO HAFDBS 3 0 3:0 Hardware updates to Access flag and Dirty state in translation tables. All other values are reserved. FEAT_HAF implements the functionality identified by the value 0b0001. FEAT_HAFDBS implements the functionality identified by the value 0b0010. FEAT_HAFT implements the functionality identified by the value 0b0011. FEAT_HDBSS implements the functionality identified by the value 0b0100. 0b0000 Hardware update of the Access flag and dirty state are not supported. 0b0001 Support for hardware update of the Access flag for Block and Page descriptors. 0b0010 As 0b0001, and adds support for hardware update of dirty state. 0b0011 As 0b0010, and adds support for hardware update of the Access flag for Table descriptors. 0b0100 As 0b0011, and adds support for hardware tracking of Dirty state Structure. RO MRS <Xt>, ID_AA64MMFR1_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64MMFR1_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64MMFR1_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_AA64MMFR1_EL1(); end; 2026-03-26 20:27:25 2026-03_rel