ID_AA64MMFR2_EL1 AArch64 Memory Model Feature Register 2 when FEAT_AA64 is implemented Provides information about the implemented memory model and memory management support in AArch64 state. For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'. Identification Registers Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3. ID_AA64MMFR2_EL1 is a 64-bit register. E0PD 63 60 63:60 Indicates support for the E0PD mechanism. All other values are reserved. FEAT_E0PD implements the functionality identified by the value 0b0001. In Armv8.4, the permitted values are 0b0000 and 0b0001. From Armv8.5, the only permitted value is 0b0001. If FEAT_E0PD is implemented, FEAT_CSV3 must be implemented. 0b0000 E0PDx mechanism is not implemented. 0b0001 E0PDx mechanism is implemented. RO EVT 59 56 59:56 Enhanced Virtualization Traps. If EL2 is implemented, indicates support for the HCR_EL2.{TTLBOS, TTLBIS, TOCU, TICAB, TID4} traps. All other values are reserved. FEAT_EVT implements the functionality identified by the value 0b0001. FEAT_EVT2 implements the functionality identified by the value 0b0010. If EL2 is not implemented, the only permitted value is 0b0000. From Armv8.5, if EL2 is implemented, the value 0b0001 is not permitted. 0b0000 HCR_EL2.{TTLBOS, TTLBIS, TOCU, TICAB, TID4} traps are not supported. 0b0001 HCR_EL2.{TOCU, TICAB, TID4} traps are supported. 0b0010 As 0b0001, and HCR_EL2.{TTLBOS, TTLBIS} traps are supported. RO BBM 55 52 55:52 Allows identification of the requirements of the hardware to have break-before-make sequences when changing block or table size for a translation. All other values are reserved. FEAT_BBML1 implements the functionality identified by the value 0b0001. FEAT_BBML2 implements the functionality identified by the value 0b0010. 0b0000 Break-before-make sequence must be used. 0b0001 Level 1 support for changing block size is supported. 0b0010 Level 2 support for changing block size is supported. RO TTL 51 48 51:48 Indicates support for TTL field in address operations. All other values are reserved. FEAT_TTL implements the functionality identified by the value 0b0001. This field affects TLBI IPAS2E1, TLBI IPAS2E1IS, TLBI IPAS2E1OS, TLBI IPAS2LE1, TLBI IPAS2LE1IS, TLBI IPAS2LE1OS, TLBI VAAE1, TLBI VAAE1IS, TLBI VAAE1OS, TLBI VAALE1, TLBI VAALE1IS, TLBI VAALE1OS, TLBI VAE1, TLBI VAE1IS, TLBI VAE1OS, TLBI VAE2, TLBI VAE2IS, TLBI VAE2OS, TLBI VAE3, TLBI VAE3IS, TLBI VAE3OS,TLBI VALE1, TLBI VALE1IS, TLBI VALE1OS, TLBI VALE2, TLBI VALE2IS, TLBI VALE2OS, TLBI VALE3, TLBI VALE3IS, TLBI VALE3OS. From Armv8.4, the value 0b0000 is not permitted. 0b0000 TLB maintenance instructions by address have bits[47:44] as RES0. 0b0001 TLB maintenance instructions by address have bits[47:44] holding the TTL field. RO 47 44 47:44 Reserved, RES0. FWB 43 40 43:40 Indicates support for HCR_EL2.FWB. All other values are reserved. FEAT_S2FWB implements the functionality identified by the value 0b0001. From Armv8.4, the value 0b0000 is not permitted. 0b0000 HCR_EL2.FWB bit is not supported. 0b0001 HCR_EL2.FWB is supported. RO IDS 39 36 39:36 Indicates the EC syndrome value in ESR_ELx.EC that is reported if an exception is generated by a read access to the feature ID space. All other values are reserved. The Feature ID space is defined as the System register space in AArch64 with op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7}, op2=={0-7}. FEAT_IDST implements the functionality identified by the value 0b0001. FEAT_IDTE3 implements the functionality identified by 0b0010. From Armv8.4, the value 0b0000 is not permitted. From Armv9.6, if EL3 is implemented, the value 0b0001 is not permitted. 0b0000 An exception which is generated by a read access to the feature ID space, other than a trap caused by HCR_EL2.TIDx, SCTLR_EL1.UCT, or SCTLR_EL2.UCT is reported by ESR_ELx.EC == 0x0. 0b0001 All exceptions generated by an AArch64 read access to the feature ID space are reported by ESR_ELx.EC == 0x18. 0b0010 As 0b0001 and introduces support for trapping ID register accesses to EL3. RO AT 35 32 35:32 Identifies support for unaligned single-copy atomicity and atomic functions. All other values are reserved. FEAT_LSE2 implements the functionality identified by the value 0b0001. From Armv8.4, the value 0b0000 is not permitted. 0b0000 Unaligned single-copy atomicity and atomic functions are not supported. 0b0001 Unaligned single-copy atomicity and atomic functions with a 16-byte address range aligned to 16-bytes are supported. RO ST 31 28 31:28 Identifies support for small translation tables. All other values are reserved. FEAT_TTST implements the functionality identified by the value 0b0001. When FEAT_SEL2 is implemented, the value 0b0000 is not permitted. 0b0000 The maximum value of the TCR_ELx.{T0SZ,T1SZ} and VTCR_EL2.T0SZ fields is 39. 0b0001 The maximum value of the TCR_ELx.{T0SZ,T1SZ} and VTCR_EL2.T0SZ fields is 48 for 4KB and 16KB granules, and 47 for 64KB granules. RO NV 27 24 27:24 Nested Virtualization. If EL2 is implemented, indicates support for the use of nested virtualization. All other values are reserved. If EL2 is not implemented, the only permitted value is 0b0000. FEAT_NV implements the functionality identified by the value 0b0001. FEAT_NV2 implements the functionality identified by the value 0b0010. In Armv8.3, if EL2 is implemented, the permitted values are 0b0000 and 0b0001. From Armv8.4, if EL2 is implemented, the permitted values are 0b0000, 0b0001, and 0b0010. 0b0000 If ID_AA64MMFR4_EL1.NV_frac != 0b0000, support for nested virtualization is described in ID_AA64MMFR4_EL1.NV_frac. Otherwise, nested virtualization is not supported. 0b0001 The HCR_EL2.{AT, NV1, NV} bits are implemented. 0b0010 The VNCR_EL2 register and the HCR_EL2.{NV2, AT, NV1, NV} bits are implemented. RO CCIDX 23 20 23:20 Support for the use of revised CCSIDR_EL1 register format. All other values are reserved. FEAT_CCIDX implements the functionality identified by the value 0b0001. From Armv8.3, the permitted values are 0b0000 and 0b0001. 0b0000 32-bit format implemented for all levels of the CCSIDR_EL1. 0b0001 64-bit format implemented for all levels of the CCSIDR_EL1. RO VARange 19 16 19:16 Indicates support for a larger virtual address. All other values are reserved. FEAT_LVA implements the functionality identified by the value 0b0001. FEAT_LVA3 implements the functionality identified by the value 0b0010. 0b0000 VMSAv8-64 supports 48-bit VAs. 0b0001 VMSAv8-64 supports 52-bit VAs when using the 64KB translation granule. The size for other translation granules is not defined by this field. 0b0010 VMSAv9-128 supports 56-bit VAs. When FEAT_D128 is implemented RO IESB 15 12 15:12 Indicates support for the IESB fields in the SCTLR_ELx and ESR_ELx registers. All other values are reserved. FEAT_IESB implements the functionality identified by the value 0b0001. 0b0000 IESB fields in the SCTLR_ELx and ESR_ELx registers is not supported. 0b0001 IESB fields in the SCTLR_ELx and ESR_ELx registers is supported. If an SError exception is taken ELx as a result of the error synchronization event generated on exception entry by the FEAT_IESB mechanism, then the PE sets ESR_ELx.IESB bit in the SError exception syndrome to 0b1. If an SError exception is taken to ELx as a result of the error synchronization event generated on exception return by the FEAT_IESB mechanism, then the PE sets the ESR_ELx.IESB bit in the SError exception syndrome to an IMPLEMENTATION DEFINED choice of 0b0 or 0b1. RO LSM 11 8 11:8 Indicates support for LSMAOE and nTLSMD bits in SCTLR_EL1 and SCTLR_EL2. All other values are reserved. FEAT_LSMAOC implements the functionality identified by the value 0b0001. 0b0000 LSMAOE and nTLSMD bits not supported. 0b0001 LSMAOE and nTLSMD bits supported. RO UAO 7 4 7:4 User Access Override. All other values are reserved. FEAT_UAO implements the functionality identified by the value 0b0001. From Armv8.2, the value 0b0000 is not permitted. 0b0000 UAO not supported. 0b0001 UAO supported. RO CnP 3 0 3:0 Indicates support for Common not Private translations. All other values are reserved. FEAT_TTCNP implements the functionality identified by the value 0b0001. From Armv8.2, the value 0b0000 is not permitted. 0b0000 Common not Private translations not supported. 0b0001 Common not Private translations supported. RO MRS <Xt>, ID_AA64MMFR2_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_AA64MMFR2_EL1()) || ImpDefBool("ID_AA64MMFR2_EL1 trapped by HCR_EL2.TID3")) && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64MMFR2_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64MMFR2_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_AA64MMFR2_EL1(); end; 2026-03-26 20:27:25 2026-03_rel