ID_AA64MMFR3_EL1 AArch64 Memory Model Feature Register 3 when FEAT_AA64 is implemented Provides information about the implemented memory model and memory management support in AArch64 state. Identification Registers Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3. ID_AA64MMFR3_EL1 is a 64-bit register. Spec_FPACC 63 60 3:0 Speculative behavior in the event of a PAC authentication failure in an implementation that includes FEAT_FPACCOMBINE. All other values are reserved. For the purpose of this definition, cached microarchitecture state is the state of caching agents such as instruction caches, data caches and TLBs which can be altered as a result of speculation caused by a mispredicted execution, but is not restored to the state prior to the speculation when the misprediction is corrected. 0b0000 The implementation does not disclose whether the speculative use of pointers processed by a PAC Authentication is materially different in terms of the impact on cached microarchitectural state between passing and failing of the PAC Authentication. 0b0001 The speculative use of pointers processed by a PAC Authentication is not materially different in terms of the impact on cached microarchitectural state between passing and failing of the PAC Authentication. RO When FEAT_FPACCOMBINE is implemented 63 60 63:60 Reserved, RES0. Otherwise ADERR 59 56 59:56 Asynchronous Device error exceptions. With ID_AA64MMFR3_EL1.SDERR, describes the PE behavior for External aborts signaled on Device memory loads. All other values are reserved. Implementation-specific exceptions to applications of this field are described in 'Taking error exceptions'. When FEAT_RASv2 is implemented and ID_AA64MMFR3_EL1.SDERR is 0b0000, the value of this field is 0b0001. When ID_AA64MMFR3_EL1.SDERR is 0b0001, the value of this field is 0b0000. When ID_AA64MMFR3_EL1.SDERR is 0b0010, the value of this field is 0b0010. When ID_AA64MMFR3_EL1.SDERR is 0b0011, the value of this field is 0b0011. FEAT_ADERR implements the functionality described by the value 0b0010. 0b0000 If FEAT_RASv2 is not implemented and ID_AA64MMFR3_EL1.SDERR is 0b0000, then the behavior is not described. Otherwise, the behavior is described by ID_AA64MMFR3_EL1.SDERR. 0b0001 All External aborts on Device memory loads are handled asynchronously. 0b0010 FEAT_ADERR is implemented. SCTLR2_ELx.EnADERR and HCRX_EL2.EnSDERR are implemented. If FEAT_ANERR is also implemented, then software should ensure that all the following apply: SCTLR2_ELx.EnADERR is set to the value of SCTLR2_ELx.EnANERR. HCRX_EL2.EnSDERR is set to the value of HCRX_EL2.EnSNERR. 0b0011 FEAT_ADERR is implemented. SCTLR2_ELx.EnADERR and HCRX_EL2.EnSDERR are implemented. If FEAT_ANERR is also implemented, then SCTLR2_ELx.EnADERR and HCRX_EL2.EnSDERR operate independently of SCTLR2_ELx.EnANERR and HCRX_EL2.EnSNERR. RO SDERR 55 52 55:52 Synchronous Device error exceptions. With ID_AA64MMFR3_EL1.ADERR, describes the PE behavior for External aborts signaled on Device memory loads. All other values are reserved. Implementation-specific exceptions to applications of this field are described in 'Taking error exceptions'. When FEAT_RASv2 is implemented and ID_AA64MMFR3_EL1.ADERR is 0b0000, the value of this field is 0b0001. When ID_AA64MMFR3_EL1.ADERR is 0b0001, the value of this field is 0b0000. When ID_AA64MMFR3_EL1.ADERR is 0b0010, the value of this field is 0b0010. When ID_AA64MMFR3_EL1.ADERR is 0b0011, the value of this field is 0b0011. FEAT_ADERR implements the functionality described by the value 0b0010. 0b0000 If FEAT_RASv2 is not implemented and ID_AA64MMFR3_EL1.ADERR is 0b0000, then the behavior is not described. Otherwise, the behavior is described by ID_AA64MMFR3_EL1.ADERR. 0b0001 All External aborts on Device memory loads are handled synchronously. 0b0010 FEAT_ADERR is implemented. SCTLR2_ELx.EnADERR and HCRX_EL2.EnSDERR are implemented. If FEAT_ANERR is also implemented, then software should ensure that all the following apply: SCTLR2_ELx.EnADERR is set to the value of SCTLR2_ELx.EnANERR. HCRX_EL2.EnSDERR is set to the value of HCRX_EL2.EnSNERR. 0b0011 FEAT_ADERR is implemented. SCTLR2_ELx.EnADERR and HCRX_EL2.EnSDERR are implemented. If FEAT_ANERR is also implemented, then SCTLR2_ELx.EnADERR and HCRX_EL2.EnSDERR operate independently of SCTLR2_ELx.EnANERR and HCRX_EL2.EnSNERR. RO 51 48 51:48 Reserved, RES0. ANERR 47 44 47:44 Asynchronous Normal error exceptions. With ID_AA64MMFR3_EL1.SNERR, describes the PE behavior for External aborts signaled on Normal memory loads. All other values are reserved. Implementation-specific exceptions to applications of this field are described in 'Taking error exceptions'. When FEAT_RASv2 is implemented and ID_AA64MMFR3_EL1.SNERR is 0b0000, the value of this field is 0b0001. When ID_AA64MMFR3_EL1.SNERR is 0b0001, the value of this field is 0b0000. When ID_AA64MMFR3_EL1.SNERR is 0b0010, the value of this field is 0b0010. When ID_AA64MMFR3_EL1.SNERR is 0b0011, the value of this field is 0b0011. FEAT_ANERR implements the functionality described by the value 0b0010. 0b0000 If FEAT_RASv2 is not implemented and ID_AA64MMFR3_EL1.SNERR is 0b0000, then the behavior is not described. Otherwise, the behavior is described by ID_AA64MMFR3_EL1.SNERR. 0b0001 All External aborts on Normal memory loads are handled asynchronously. 0b0010 FEAT_ANERR is implemented. SCTLR2_ELx.EnANERR and HCRX_EL2.EnSNERR are implemented. If FEAT_ADERR is also implemented, then software should ensure that all the following apply: SCTLR2_ELx.EnANERR is set to the value of SCTLR2_ELx.EnADERR. HCRX_EL2.EnSNERR is set to the value of HCRX_EL2.EnSDERR. 0b0011 FEAT_ANERR is implemented. SCTLR2_ELx.EnANERR and HCRX_EL2.EnSNERR are implemented. If FEAT_ADERR is also implemented, then SCTLR2_ELx.EnANERR and HCRX_EL2.EnSNERR operate independently of SCTLR2_ELx.EnADERR and HCRX_EL2.EnSDERR. RO SNERR 43 40 43:40 Synchronous Normal error exceptions. With ID_AA64MMFR3_EL1.ANERR, describes the PE behavior for External aborts signaled on Normal memory loads. All other values are reserved. Implementation-specific exceptions to applications of this field are described in 'Taking error exceptions'. When FEAT_RASv2 is implemented and ID_AA64MMFR3_EL1.ANERR is 0b0000, the value of this field is 0b0001. When ID_AA64MMFR3_EL1.ANERR is 0b0001, the value of this field is 0b0000. When ID_AA64MMFR3_EL1.ANERR is 0b0010, the value of this field is 0b0010. When ID_AA64MMFR3_EL1.ANERR is 0b0011, the value of this field is 0b0011. FEAT_ANERR implements the functionality described by the value 0b0010. 0b0000 If FEAT_RASv2 is not implemented and ID_AA64MMFR3_EL1.ANERR is 0b0000, then the behavior is not described. Otherwise, the behavior is described by ID_AA64MMFR3_EL1.ANERR. 0b0001 All External aborts on Normal memory loads are handled synchronously. 0b0010 FEAT_ANERR is implemented. SCTLR2_ELx.EnANERR and HCRX_EL2.EnSNERR are implemented. If FEAT_ADERR is also implemented, then software should ensure that all the following apply: SCTLR2_ELx.EnANERR is set to the value of SCTLR2_ELx.EnADERR. HCRX_EL2.EnSNERR is set to the value of HCRX_EL2.EnSDERR. 0b0011 FEAT_ANERR is implemented. SCTLR2_ELx.EnANERR and HCRX_EL2.EnSNERR are implemented. If FEAT_ADERR is also implemented, then SCTLR2_ELx.EnANERR and HCRX_EL2.EnSNERR operate independently of SCTLR2_ELx.EnADERR and HCRX_EL2.EnSDERR. RO D128_2 39 36 39:36 128-bit translation table descriptor at stage 2. Indicates support for 128-bit translation table descriptor at stage 2. All other values are reserved. 0b0000 128-bit translation table descriptor Extension at stage 2 is not supported. 0b0001 128-bit translation table descriptor Extension at stage 2 is supported. RO D128 35 32 35:32 128-bit translation table descriptor. Indicates support for 128-bit translation table descriptor. All other values are reserved. 0b0000 128-bit translation table descriptor Extension is not supported. 0b0001 128-bit translation table descriptor Extension is supported. RO MEC 31 28 31:28 Indicates support for Memory Encryption Contexts. All other values are reserved. FEAT_MEC implements the functionality identified by the value 0b0001. 0b0000 Memory Encryption Contexts is not supported. 0b0001 Memory Encryption Contexts is supported, with multiple contexts in the Realm physical address space. RO AIE 27 24 27:24 Attribute Indexing. Indicates support for the Attribute Index Enhancement. All other values are reserved. FEAT_AIE implements the functionality identified by the value 0b0001. 0b0000 The Attribute Index Enhancement is not supported. 0b0001 The Attribute Index Enhancement at stage 1 is supported. RO S2POE 23 20 23:20 Stage 2 Permission Overlay. Indicates support for Permission Overlay at stage 2. All other values are reserved. FEAT_S2POE implements the functionality identified by the value 0b0001. 0b0000 Permission Overlay at stage 2 is not supported. 0b0001 Permission Overlay at stage 2 is supported. RO S1POE 19 16 19:16 Stage 1 Permission Overlay. Indicates support for Permission Overlay at stage 1. All other values are reserved. FEAT_S1POE implements the functionality identified by the value 0b0001. 0b0000 Permission Overlay at stage 1 is not supported. 0b0001 Permission Overlay at stage 1 is supported. RO S2PIE 15 12 15:12 Stage 2 Permission Indirection. Indicates support for Permission Indirection at stage 2. All other values are reserved. FEAT_S2PIE implements the functionality identified by the value 0b0001. 0b0000 Permission Indirection at stage 2 is not supported. 0b0001 Permission Indirection at stage 2 is supported. RO S1PIE 11 8 11:8 Stage 1 Permission Indirection. Indicates support for Permission Indirection at stage 1. All other values are reserved. FEAT_S1PIE implements the functionality identified by the value 0b0001. 0b0000 Permission Indirection at stage 1 is not supported. 0b0001 Permission Indirection at stage 1 is supported. RO SCTLRX 7 4 7:4 SCTLR Extension. Indicates support for extension of SCTLR_ELx. All other values are reserved. From Armv8.9, the value 0b0000 is not permitted. FEAT_SCTLR2 implements the functionality described by the value 0b0001. 0b0000 SCTLR2_EL1, SCTLR2_EL2, SCTLR2_EL3 registers, and their associated trap controls are not implemented. 0b0001 SCTLR2_EL1, SCTLR2_EL2, SCTLR2_EL3 resisters, and their associated trap controls are implemented. RO TCRX 3 0 3:0 TCR Extension. Indicates support for extension of TCR_ELx. All other values are reserved. From Armv8.9, the value 0b0000 is not permitted. FEAT_TCR2 implements the functionality described by the value 0b0001. 0b0000 TCR2_EL1, TCR2_EL2, and their associated trap controls are not implemented. 0b0001 TCR2_EL1, TCR2_EL2, and their associated trap controls are implemented. RO MRS <Xt>, ID_AA64MMFR3_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_AA64MMFR3_EL1()) || ImpDefBool("ID_AA64MMFR3_EL1 trapped by HCR_EL2.TID3")) && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64MMFR3_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64MMFR3_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_AA64MMFR3_EL1(); end; 2026-03-26 20:27:25 2026-03_rel