ID_AA64MMFR4_EL1 AArch64 Memory Model Feature Register 4 when FEAT_AA64 is implemented Provides additional information about implemented memory model and memory management support in AArch64. Identification Registers Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3. ID_AA64MMFR4_EL1 is a 64-bit register. 63 48 63:48 Reserved, RES0. SRMASK 47 44 47:44 Indicates support for bitwise write masks for the following registers: ACTLR_EL1. CPACR_EL1. SCTLR_EL1. SCTLR2_EL1. TCR_EL1. TCR2_EL1. ACTLR_EL2. CPTR_EL2. SCTLR_EL2. SCTLR2_EL2. TCR_EL2. TCR2_EL2. FEAT_SRMASK implements the functionality identified by the value 0b0001. From Armv9.6, the value 0b0000 is not permitted. 0b0000 Bitwise write masks for the specified registers are not supported. 0b0001 Bitwise write masks for the specified registers are supported. RO 43 40 43:40 Reserved, RES0. E3DSE 39 36 39:36 Delegated SError exceptions from EL3. Describes support for delegated SError injection from EL3. All other values are reserved. FEAT_E3DSE implements the functionality described by the value 0b0001. 0b0000 FEAT_E3DSE is not implemented. 0b0001 FEAT_E3DSE is implemented. The following are implemented: Register fields SCR_EL3.DSE and SCR_EL3.EnDSE. Registers VSESR_EL3 and VDISR_EL3. RO 35 32 35:32 Reserved, RES0. RMEGDI 31 28 31:28 RME Granular Data Isolation. All other values are reserved. FEAT_RME_GDI implements the functionality described by the value 0b0001. 0b0000 The Granular Data isolation GPI encodings are reserved. 0b0001 The Granular Data Isolation GPI encodings can be configured to be either reserved or No Access from this PE. RO E2H0 27 24 3:0 Indicates support for programming HCR_EL2.E2H. All other values are reserved. If FEAT_NV is not implemented, then the value 0b1110 is not permitted. If FEAT_E2H0 is implemented and FEAT_VHE is not implemented, then HCR_EL2.E2H is RES0. If FEAT_E2H0 is implemented and FEAT_VHE is implemented, then HCR_EL2.E2H can be programmed to 0 or 1. If FEAT_E2H0 is not implemented then: FEAT_VHE is implemented. HCR_EL2.E2H is RES1 and behaves as though it is 1. 0b0000 FEAT_E2H0 is implemented. 0b1110 FEAT_E2H0 is not implemented. HCR_EL2.NV1 is RES0. 0b1111 FEAT_E2H0 is not implemented. RO When FEAT_AA64EL2 is implemented 27 24 27:24 Reserved, RES0. Otherwise NV_frac 23 20 23:20 Indicates support for a subset of FEAT_NV and FEAT_NV2 behaviors. FEAT_NV2p1 implements the functionality indicated by the value 0b0010. 0b0000 Support for FEAT_NV and FEAT_NV2 is described in ID_AA64MMFR2_EL1.NV. 0b0001 FEAT_NV and FEAT_NV2 are implemented, but all of the following apply: ID_AA64MMFR2_EL1.NV is 0b0000. Programming HCR_EL2.{NV, NV2} to {1, 0} behaves as {1, 1}. 0b0010 As 0b0001 and adds stateful bits in specified _EL1 registers for software usage under nested virtualization. RO FGWTE3 19 16 19:16 Indicates support for Fine Grained Write Trap EL3 feature. All other values are reserved. FEAT_FGWTE3 implements the functionality identified by the value 0b0001. 0b0000 Fine Grained Write Trap EL3 is not supported. 0b0001 Fine Grained Write Trap EL3 is supported. RO HACDBS 15 12 15:12 Support for Hardware accelerator for cleaning Dirty state. All other values are reserved. FEAT_HACDBS implements the functionality identified by the value 0b0001. 0b0000 Hardware accelerator for cleaning Dirty state is not supported. 0b0001 Hardware accelerator for cleaning Dirty state is supported. RO ASID2 11 8 11:8 Indicates support for concurrent use of two ASIDs. All other values are reserved. From Armv9.5, the value 0b0000 is not permitted. 0b0000 FEAT_ASID2 is not implemented. 0b0001 FEAT_ASID2 is implemented. RO EIESB 7 4 3:0 Early Implicit Error Synchronization event. Indicates whether the implicit Error synchronization event inserted on taking an exception to ELx when SCTLR_ELx.IESB is 1 is inserted before or after the exception is taken. All other values are reserved. This field describes the PE behavior on taking an exception to ELx when SCTLR_ELx.IESB is 1. This field does not describe the behavior when SCTLR_ELx.IESB is 0. The behavior described by this field only applies for the conditions described above. For example, if ID_AA64MMFR4_EL1.EIESB reads as 0b0001, then it does not describe the behavior when SError exceptions are not routed to EL3, or when FEAT_DoubleFault is implemented and the Effective value of SCR_EL3.NMEA is 0. Inserting the event before the exception is taken means that if the Error synchronization event causes an SError exception to become pending, and SError exceptions are not masked and not disabled, then the SError exception is taken in place of the original exception. When FEAT_IESB is not implemented, the only permitted value of this field is 0b0000. 0b1111 When FEAT_IESB is implemented and enabled, SError exceptions are routed to EL3, and either FEAT_DoubleFault is not implemented or the Effective value of SCR_EL3.NMEA is 1, an implicit Error synchronization event might be inserted after an exception is taken to EL3, unless that exception is also an SError exception. 0b0000 FEAT_IESB is not implemented, or behavior is not described. 0b0001 When FEAT_IESB is implemented and enabled, SError exceptions are routed to EL3, and either FEAT_DoubleFault is not implemented or the Effective value of SCR_EL3.NMEA is 1, an implicit Error synchronization event is inserted before an exception taken to EL3, unless that exception is also an SError exception. 0b0010 As 0b0001, and also: When FEAT_IESB is implemented and enabled, SError exceptions are routed to EL1, and either FEAT_DoubleFault2 is not implemented or the Effective value of SCTLR2_EL1.NMEA is 1, an implicit Error synchronization event is inserted before an exception taken to EL1, unless that exception is also an SError exception. When FEAT_IESB is implemented and enabled, SError exceptions are routed to EL2, and either FEAT_DoubleFault2 is not implemented or the Effective value of SCTLR2_EL2.NMEA is 1, an implicit Error synchronization event is inserted before an exception taken to EL2, unless that exception is also an SError exception. 0b0011 When FEAT_IESB is implemented and enabled, an implicit Error synchronization event is inserted before taking an exception other than an SError exception, regardless of the Effective values of SCR_EL3.NMEA and SCTLR2_ELx.NMEA. RO When FEAT_IESB is implemented 7 4 7:4 Reserved, RES0. Otherwise PoPS 3 0 3:0 Support for the clean and invalidate to the Point of Physical Storage instructions: DC CIVAPS. If FEAT_MTE2 is implemented, DC CIGDVAPS. FEAT_PoPS implements the functionality described by the value 0b0001. All other values are reserved. 0b0000 The System instructions to clean and invalidate to the Point of Physical Storage are not implemented. 0b0001 The specified System instructions to clean and invalidate to the Point of Physical Storage are implemented. RO MRS <Xt>, ID_AA64MMFR4_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_AA64MMFR4_EL1()) || ImpDefBool("ID_AA64MMFR4_EL1 trapped by HCR_EL2.TID3")) && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64MMFR4_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64MMFR4_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_AA64MMFR4_EL1(); end; 2026-03-26 20:27:25 2026-03_rel