ID_AA64PFR0_EL1
AArch64 Processor Feature Register 0
when FEAT_AA64 is implemented
Provides additional information about implemented PE features in AArch64 state.
For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.
Identification Registers
The external register EDPFR gives information from this register.
ID_AA64PFR0_EL1 is a 64-bit register.
CSV3
63
60
63:60
Speculative use of faulting data.
All other values are reserved.
FEAT_CSV3 implements the functionality identified by the value 0b0001.
If FEAT_E0PD is implemented, FEAT_CSV3 must be implemented.
From Armv8.5, the value 0b0000 is not permitted.
0b0000
This PE does not disclose whether data loaded or read from a register under speculation where the data load or register read would not be permitted architecturally, can be used by instructions newer than the load or register read in a manner that allows the value of the inaccessible data to be recovered by code architecturally executed.
0b0001
Data loaded or read from a register under speculation where the data load or register read would not be permitted architecturally, cannot be used by instructions newer than the load or register read in a manner that allows the value of the inaccessible data to be recovered by code architecturally executed.
RO
CSV2
59
56
59:56
Speculative use of out of context prediction resources.
All other values are reserved.
FEAT_CSV2 implements the functionality identified by the value 0b0001.
FEAT_CSV2_2 implements the functionality identified by the value 0b0010.
FEAT_CSV2_3 implements the functionality identified by the feature 0b0011.
From Armv8.5, the value 0b0000 is not permitted.
0b0000
The implementation does not disclose whether FEAT_CSV2 is implemented.
0b0001
FEAT_CSV2 is implemented, but FEAT_CSV2_2 and FEAT_CSV2_3 are not implemented.
ID_AA64PFR1_EL1.CSV2_frac determines whether either or both of FEAT_CSV2_1p1 or FEAT_CSV2_1p2 are implemented.
0b0010
FEAT_CSV2_2 is implemented, but FEAT_CSV2_3 is not implemented.
0b0011
FEAT_CSV2_3 is implemented.
RO
RME
55
52
55:52
Realm Management Extension (RME).
All other values are reserved.
FEAT_RME implements the functionality identified by the value 0b0001.
FEAT_RME_GPC2 implements the functionality identified by the value 0b0010.
FEAT_RME_GPC3 implements the functionality identified by the value 0b0011.
0b0000
Realm Management Extension not implemented.
0b0001
RMEv1 is implemented.
0b0010
As 0b0001, and adds support for the GPC2 Extension.
0b0011
As 0b0010, and adds support for the GPC3 Extension.
RO
DIT
51
48
51:48
Data Independent Timing.
All other values are reserved.
FEAT_DIT implements the functionality identified by the value 0b0001.
From Armv8.4, the value 0b0000 is not permitted.
0b0000
AArch64 does not guarantee constant execution time of any instructions.
0b0001
AArch64 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions.
RO
AMU
47
44
47:44
Indicates support for Activity Monitors Extension.
All other values are reserved.
FEAT_AMUv1 implements the functionality identified by the value 0b0001.
FEAT_AMUv1p1 implements the functionality identified by the value 0b0010.
In Armv8.0, the only permitted value is 0b0000.
In Armv8.4, the permitted values are 0b0000 and 0b0001.
From Armv8.6, the permitted values are 0b0000, 0b0001, and 0b0010.
0b0000
Activity Monitors Extension is not implemented.
0b0001
FEAT_AMUv1 is implemented.
0b0010
FEAT_AMUv1p1 is implemented. As 0b0001 and adds support for virtualization of the activity monitor event counters.
RO
MPAM
43
40
43:40
Indicates the major version number of support for the MPAM Extension.
All other values are reserved.
When combined with the minor version number from ID_AA64PFR1_EL1.MPAM_frac, the "major.minor" version is:
MPAM Extension versionMPAMMPAM_frac
Not implemented.0b00000b0000
v0.1 is implemented.0b00000b0001
v1.0 is implemented.0b00010b0000
v1.1 is implemented.0b00010b0001
For more information, see 'The Memory Partitioning and Monitoring (MPAM) Extension'.
0b0000
The major version number of the MPAM extension is 0.
0b0001
The major version number of the MPAM extension is 1.
RO
SEL2
39
36
39:36
Secure EL2.
All other values are reserved.
FEAT_SEL2 implements the functionality identified by the value 0b0001.
From Armv8.4, if Secure state and EL2 are implemented, the value 0b0000 is not permitted.
From Armv8.4, if Secure state is not implemented, or if EL2 is not implemented, the only permitted value is 0b0000.
0b0000
Secure EL2 is not implemented.
0b0001
Secure EL2 is implemented.
RO
SVE
35
32
35:32
Scalable Vector Extension.
All other values are reserved.
FEAT_SVE implements the functionality identified by the value 0b0001.
If implemented, refer to ID_AA64ZFR0_EL1 for information about which SVE instructions are available.
0b0000
SVE architectural state and programmers' model are not implemented.
0b0001
SVE architectural state and programmers' model are implemented.
RO
RAS
31
28
31:28
RAS Extension version.
All other values are reserved.
FEAT_RAS implements the functionality identified by the value 0b0001.
FEAT_DoubleFault implements the functionality identified by the value 0b0010.
When ERRIDR_EL1.NUM is zero:
If FEAT_DoubleFault is not implemented, then this field is permitted to have the value 0b0001, regardless of whether FEAT_RASv1p1 or FEAT_RASv2 are implemented.
If FEAT_DoubleFault is implemented, then this field is permitted to have the value 0b0010, regardless of whether FEAT_RASv2 is implemented.
When ERRIDR_EL1.NUM is nonzero:
FEAT_RASv1p1 implements the functionality identified by the value 0b0010.
FEAT_RASv2 implements the functionality identified by the value 0b0011.
From Armv8.2, the value 0b0000 is not permitted.
From Armv8.4, if FEAT_DoubleFault is implemented or ERRIDR_EL1.NUM is nonzero, the value 0b0001 is not permitted.
When the value of this field is 0b0001, ID_AA64PFR1_EL1.RAS_frac indicates whether FEAT_RASv1p1 is implemented.From Armv8.9, if ERRIDR_EL1.NUM is nonzero, the value 0b0010 is not permitted.
0b0000
No RAS Extension.
0b0001
Support for the Reliability, Availability, and Serviceability Extension is implemented. The ESB instruction and the Error synchronization event are supported.
0b0010
As 0b0001, and adds support for:
If EL3 is implemented, FEAT_DoubleFault.
Additional ERXMISC<m>_EL1 System registers.
Additional System registers ERXPFGCDN_EL1, ERXPFGCTL_EL1, and ERXPFGF_EL1, and the SCR_EL3.FIEN and HCR_EL2.FIEN trap controls, to support the optional RAS Common Fault Injection Model Extension.
Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to ERR<n>STATUS and support for the optional RAS Timestamp and RAS Common Fault Injection Model Extensions.
0b0011
As 0b0010 and adds support for:
The error group status register, ERXGSR_EL1.
The SCR_EL3.TWERR write trap control for error record System registers.
Additional fields in ESR_ELx.ISS for error exceptions.
Error records accessed through System registers conform to either RAS System Architecture v1.1 or RAS System Architecture v2.
RO
GIC
27
24
27:24
System register GIC CPU interface.
All other values are reserved.
0b0000
GIC CPU interface system registers not implemented.
0b0001
System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported.
0b0011
System register interface to version 4.1 of the GIC CPU interface is supported.
RO
AdvSIMD
23
20
23:20
Advanced SIMD.
All other values are reserved.
This field must have the same value as the FP field.
The permitted values are:
0b0000 in an implementation with Advanced SIMD support that does not include the FEAT_FP16 extension.
0b0001 in an implementation with Advanced SIMD support that includes the FEAT_FP16 extension.
0b1111 in an implementation without Advanced SIMD support.
0b0000
Advanced SIMD is implemented, including support for the following SISD and SIMD operations:
Integer byte, halfword, word and doubleword element operations.
Single-precision and double-precision floating-point arithmetic.
Conversions between single-precision and half-precision data types, and double-precision and half-precision data types.
0b0001
As for 0b0000, and also includes support for half-precision floating-point arithmetic.
0b1111
Advanced SIMD is not implemented.
RO
FP
19
16
19:16
Floating-point.
All other values are reserved.
This field must have the same value as the AdvSIMD field.
The permitted values are:
0b0000 in an implementation with floating-point support that does not include the FEAT_FP16 extension.
0b0001 in an implementation with floating-point support that includes the FEAT_FP16 extension.
0b1111 in an implementation without floating-point support.
0b0000
Floating-point is implemented, and includes support for:
Single-precision and double-precision floating-point types.
Conversions between single-precision and half-precision data types, and double-precision and half-precision data types.
0b0001
As for 0b0000, and also includes support for half-precision floating-point arithmetic.
0b1111
Floating-point is not implemented.
RO
EL3
15
12
15:12
EL3 Exception level handling.
All other values are reserved.
The value 0b0010 is not permitted in Armv9-A implementations.
0b0000
EL3 is not implemented.
0b0001
EL3 can be executed in AArch64 state only.
0b0010
EL3 can be executed in either AArch64 or AArch32 state.
RO
EL2
11
8
11:8
EL2 Exception level handling.
All other values are reserved.
The value 0b0010 is not permitted in Armv9-A implementations.
0b0000
EL2 is not implemented.
0b0001
EL2 can be executed in AArch64 state only.
0b0010
EL2 can be executed in either AArch64 or AArch32 state.
RO
EL1
7
4
7:4
EL1 Exception level handling.
All other values are reserved.
The value 0b0010 is not permitted in Armv9-A implementations.
0b0001
EL1 can be executed in AArch64 state only.
0b0010
EL1 can be executed in either AArch64 or AArch32 state.
RO
EL0
3
0
3:0
EL0 Exception level handling.
All other values are reserved.
0b0001
EL0 can be executed in AArch64 state only.
0b0010
EL0 can be executed in either AArch64 or AArch32 state.
RO
MRS <Xt>, ID_AA64PFR0_EL1
if !IsFeatureImplemented(FEAT_AA64) then
UnimplementedIDRegister();
elsif PSTATE.EL == EL0 then
if IsFeatureImplemented(FEAT_IDST) then
if EL2Enabled() && HCR_EL2().TGE == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
else
AArch64_SystemAccessTrap(EL1, 0x18);
end;
else
Undefined();
end;
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then
Undefined();
elsif EL2Enabled() && HCR_EL2().TID3 == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
X{64}(t) = ID_AA64PFR0_EL1();
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then
Undefined();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
X{64}(t) = ID_AA64PFR0_EL1();
end;
elsif PSTATE.EL == EL3 then
X{64}(t) = ID_AA64PFR0_EL1();
end;
2026-03-26 20:27:25
2026-03_rel