ID_AA64PFR1_EL1
AArch64 Processor Feature Register 1
when FEAT_AA64 is implemented
Provides additional information about implemented PE features in AArch64 state.
For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.
Identification Registers
ID_AA64PFR1_EL1 is a 64-bit register.
PFAR
63
60
63:60
Support for physical fault address registers, FEAT_PFAR.
All other values are reserved.
FEAT_PFAR implements the functionality identified by the value 0b0001.
0b0000
FEAT_PFAR is not implemented.
0b0001
FEAT_PFAR is implemented. Includes support for the PFAR_ELx and, if EL3 is implemented, MFAR_EL3 registers.
RO
DF2
59
56
59:56
Support for error exception routing extensions, FEAT_DoubleFault2.
All other values are reserved.
FEAT_DoubleFault2 implements the functionality identified by the value 0b0001.
0b0000
FEAT_DoubleFault2 is not implemented.
This does not mean that FEAT_DoubleFault, as identified by ID_AA64PFR0_EL1.RAS >= 0b0010, is not implemented.
0b0001
FEAT_DoubleFault2 is implemented. As ID_AA64PFR0_EL1.RAS == 0b0010, and also includes support for routing error exceptions:
Traps for masked error exceptions, HCRX_EL2.TMEA and SCR_EL3.TMEA.
Additional controls for masking SError exceptions, SCTLR2_EL1.NMEA, and SCTLR2_EL2.NMEA.
Additional controls for taking external aborts to the SError exception vector, SCTLR2_EL1.EASE and SCTLR2_EL2.EASE.
RO
MTEX
55
52
55:52
Support for additional MTE tag checking modes.
All other values are reserved.
This field is valid only if ID_AA64PFR1_EL1.MTE >= 0b0010.
FEAT_MTE_NO_ADDRESS_TAGS and FEAT_MTE_CANONICAL_TAGS implement the functionality identified by the value 0b0001.
If FEAT_MTE2 is not implemented, the value 0b0001 is not permitted.
From Armv8.9, if FEAT_MTE2 is implemented, the value 0b0000 is not permitted.
0b0000
Canonical Tag checking and Memory tagging with Address tagging disabled are not supported.
0b0001
The following additional tag checking modes for MTE are supported:
Canonical Tag checking.
Memory tagging with Address tagging disabled.
RO
THE
51
48
51:48
Support for Translation Hardening Extension.
All other values are reserved.
FEAT_THE implements the functionality identified by the value 0b0001.
0b0000
Translation Hardening Extension is not implemented.
0b0001
The RCW and RCWS instructions, their associated registers and traps are supported.
If EL2 is implemented, the AssuredOnly check, TopLevel check, and their associated controls are implemented.
If EL2 and FEAT_GCS are implemented, VTCR_EL2.GCSH is implemented.
RO
GCS
47
44
47:44
Support for Guarded Control Stack.
All other values are reserved.
FEAT_GCS implements the functionality identified by the value 0b0001.
0b0000
Guarded Control Stack is not implemented.
0b0001
Guarded Control Stack is implemented.
RO
MTE_frac
43
40
43:40
Support for Asynchronous reporting of a Tag Check Fault.
All other values are reserved.
This field is valid only if ID_AA64PFR1_EL1.MTE >= 0b0010.
FEAT_MTE_ASYNC implements the functionality identified by the value 0b0000.
If FEAT_MTE_ASYM_FAULT is implemented this field must be 0b0000.
0b0000
Asynchronous reporting of a Tag Check Fault is supported.
0b1111
Asynchronous reporting of a Tag Check Fault is not supported.
RO
NMI
39
36
39:36
Non-maskable Interrupt. Indicates support for Non-maskable interrupts.
All other values are reserved.
FEAT_NMI implements the functionality identified by the value 0b0001.
From Armv8.8, the value 0b0000 is not permitted.
0b0000
SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT with its associated instructions are not supported.
0b0001
SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT with its associated instructions are supported.
RO
CSV2_frac
35
32
35:32
CSV2 fractional field.
All other values are reserved.
FEAT_CSV2_1p1 implements the functionality identified by the value 0b0001.
FEAT_CSV2_1p2 implements the functionality identified by the value 0b0010.
From Armv8.0, the permitted values are 0b0000, 0b0001, and 0b0010.
The values 0b0001 and 0b0010 are permitted only when ID_AA64PFR0_EL1.CSV2 is 0b0001.
0b0000
Either ID_AA64PFR0_EL1.CSV2 is not 0b0001, or the implementation does not disclose whether FEAT_CSV2_1p1 is implemented.
FEAT_CSV2_1p2 is not implemented.
0b0001
FEAT_CSV2_1p1 is implemented, but FEAT_CSV2_1p2 is not implemented.
0b0010
FEAT_CSV2_1p2 is implemented.
RO
RNDR_trap
31
28
31:28
Random Number trap to EL3 field.
All other values are reserved.
FEAT_RNG_TRAP implements the functionality identified by the value 0b0001.
0b0000
Trapping of RNDR and RNDRRS to EL3 is not supported.
0b0001
Trapping of RNDR and RNDRRS to EL3 is supported.
SCR_EL3.TRNDR is present.
RO
SME
27
24
27:24
Scalable Matrix Extension.
All other values are reserved.
FEAT_SME implements the functionality identified by the value 0b0001.
FEAT_SME2 implements the functionality identified by the value 0b0010.
From Armv9.2, the permitted values are 0b0000, 0b0001, and 0b0010.
If implemented, refer to ID_AA64SMFR0_EL1 and ID_AA64ZFR0_EL1 for information about which SME and SVE instructions are available.
0b0000
SME architectural state and programmers' model are not implemented.
0b0001
SME architectural state and programmers' model are implemented.
0b0010
As 0b0001, plus the SME2 ZT0 register.
RO
23
20
23:20
Reserved, RES0.
MPAM_frac
19
16
19:16
Indicates the minor version number of support for the MPAM Extension.
All other values are reserved.
When combined with the major version number from ID_AA64PFR0_EL1.MPAM, The combined "major.minor" version is:
MPAM Extension versionMPAMMPAM_frac
Not implemented.0b00000b0000
v0.1 is implemented.0b00000b0001
v1.0 is implemented.0b00010b0000
v1.1 is implemented.0b00010b0001
For more information, see 'The Memory Partitioning and Monitoring (MPAM) Extension'.
0b0000
The minor version number of the MPAM extension is 0.
0b0001
The minor version number of the MPAM extension is 1.
RO
RAS_frac
15
12
15:12
RAS Extension fractional field.
All other values are reserved.
FEAT_RAS implements the functionality identified by the value 0b0000.
When ERRIDR_EL1.NUM is zero, this field is permitted to have the value 0b0000, regardless of whether FEAT_RASv1p1 is implemented.
When ERRIDR_EL1.NUM is nonzero, FEAT_RASv1p1 implements the functionality identified by the value 0b0001.
This field is valid only if ID_AA64PFR0_EL1.RAS == 0b0001.
0b0000
If ID_AA64PFR0_EL1.RAS == 0b0001, support for the Reliability, Availability, and Serviceability Extension is implemented.
0b0001
If ID_AA64PFR0_EL1.RAS == 0b0001, as 0b0000 and adds support for:
Additional ERXMISC<m>_EL1 System registers.
Additional System registers ERXPFGCDN_EL1, ERXPFGCTL_EL1, and ERXPFGF_EL1, and the SCR_EL3.FIEN and HCR_EL2.FIEN trap controls, to support the optional RAS Common Fault Injection Model Extension.
Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to ERR<n>STATUS, and support for the optional RAS Timestamp and RAS Common Fault Injection Model Extensions.
RO
MTE
11
8
11:8
Support for the Memory Tagging Extension.
All other values are reserved.
FEAT_MTE implements the functionality identified by the value 0b0001.
FEAT_MTE2 implements the functionality identified by the value 0b0010.
FEAT_MTE3 implements the functionality identified by the value 0b0011.
From Armv8.7, when the value of this field is >= 0b0010, ID_AA64PFR2_EL1.MTEPERM indicates support for FEAT_MTE_PERM.
From Armv8.7, when the value of this field is >= 0b0010, the following fields indicate support for FEAT_MTE4:
ID_AA64PFR1_EL1.MTEX
ID_AA64PFR2_EL1.MTEFAR
ID_AA64PFR2_EL1.MTESTOREONLY
0b0000
Memory Tagging Extension is not implemented.
0b0001
Instruction-only Memory Tagging Extension is implemented.
0b0010
As 0b0001, and adds:
Support for in-memory Allocation tags.
Support for synchronous tag checking.
Optional support for Asynchronous reporting of a Tag Check Fault, identified as FEAT_MTE_ASYNC.
Support for FEAT_MTE_ASYNC is indicated by ID_AA64PFR1_EL1.MTE_frac.
0b0011
As 0b0010, except that support for FEAT_MTE_ASYNC is mandatory, and adds support for Asymmetric Tag Check Fault handling, identified as FEAT_MTE_ASYM_FAULT.
RO
SSBS
7
4
7:4
Speculative Store Bypassing controls in AArch64 state.
All other values are reserved.
FEAT_SSBS implements the functionality identified by the value 0b0001.
FEAT_SSBS2 implements the functionality identified by the value 0b0010.
0b0000
AArch64 provides no mechanism to control the use of Speculative Store Bypassing.
0b0001
AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe.
0b0010
As 0b0001, and adds the MSR and MRS instructions to directly read and write the PSTATE.SSBS field.
RO
BT
3
0
3:0
Branch Target Identification mechanism support in AArch64 state.
All other values are reserved.
FEAT_BTI implements the functionality identified by the value 0b0001.
From Armv8.5, the value 0b0000 is not permitted.
0b0000
The Branch Target Identification mechanism is not implemented.
0b0001
The Branch Target Identification mechanism is implemented.
RO
MRS <Xt>, ID_AA64PFR1_EL1
if !IsFeatureImplemented(FEAT_AA64) then
UnimplementedIDRegister();
elsif PSTATE.EL == EL0 then
if IsFeatureImplemented(FEAT_IDST) then
if EL2Enabled() && HCR_EL2().TGE == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
else
AArch64_SystemAccessTrap(EL1, 0x18);
end;
else
Undefined();
end;
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then
Undefined();
elsif EL2Enabled() && HCR_EL2().TID3 == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
X{64}(t) = ID_AA64PFR1_EL1();
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then
Undefined();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
X{64}(t) = ID_AA64PFR1_EL1();
end;
elsif PSTATE.EL == EL3 then
X{64}(t) = ID_AA64PFR1_EL1();
end;
2026-03-26 20:27:25
2026-03_rel