ID_AA64SMFR0_EL1 SME Feature ID Register 0 Provides information about the implemented features of the AArch64 Scalable Matrix Extension. The fields in this register do not follow the standard ID scheme. See Alternative ID scheme used for ID_AA64SMFR0_EL1 and ID_AA64FPFR0_EL1. Identification Registers Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3. ID_AA64SMFR0_EL1 is a 64-bit register. FA64 63 63 63 Indicates support at each Exception Level for execution of the full AArch64 Advanced SIMD and SVE instruction sets when the PE is in Streaming SVE mode. FEAT_SME_FA64 implements the functionality identified by the value 1. 0b0 Only those AArch64 instructions defined as being legal can be executed in streaming SVE mode. 0b1 All implemented AArch64 instructions are legal for execution in Streaming SVE mode, when enabled by SMCR_EL1.FA64, SMCR_EL2.FA64, and SMCR_EL3.FA64. RO 62 61 62:61 Reserved, RES0. LUTv2 60 60 60 Indicates support for the following additional variants of SME2 lookup table LUTI4 and MOVT instructions: A LUTI4 instruction with 8-bit result elements, two consecutively numbered source vectors, and four consecutively numbered destination vectors. If FEAT_SME2p1 is implemented, a LUTI4 instruction with 8-bit result elements, two consecutively numbered source vectors, and four destination vectors with strided register numbering. A MOVT instruction that copies a single Z source vector to ZT0. All other values are reserved. FEAT_SME_LUTv2 implements the functionality identified by the value 1. 0b0 The specified instructions are not implemented by this control. 0b1 The specified instructions are implemented. RO SMEver 59 56 3:0 Indicates support for SME instructions. All other values are reserved. FEAT_SME2 implements the functionality identified by the value 0b0001. FEAT_SME2p1 implements the functionality identified by the value 0b0010. From Armv9.4, the value 0b0001 is not permitted. FEAT_SME2p2 implements the functionality identified by 0b0011. From Armv9.6, the values 0b0000 and 0b0010 are not permitted. 0b0000 The mandatory SME instructions are implemented. 0b0001 As 0b0000, and adds the mandatory SME2 instructions. 0b0010 As 0b0001, and adds the mandatory SME2.1 instructions. 0b0011 As 0b0010, and adds the mandatory SME2.2 instructions. RO When FEAT_SME is implemented 59 56 59:56 Reserved, RES0. Otherwise I16I64 55 52 55:52 Indicates support for the following SME instructions that accumulate into 64-bit integer elements in the ZA array: The variants of the ADDHA, ADDVA, SMOPA, SMOPS, SUMOPA, SUMOPS, UMOPA, UMOPS, USMOPA, and USMOPS instructions that accumulate into 64-bit integer tiles. When FEAT_SME2 is implemented, the variants of the ADD, ADDA, SDOT, SMLALL, SMLSLL, SUB, SUBA, SVDOT, UDOT, UMLALL, UMLSLL, and UVDOT instructions that accumulate into 64-bit integer elements in ZA array vectors. All other values are reserved. FEAT_SME_I16I64 implements the functionality identified by the value 0b1111. 0b0000 The specified instructions are not implemented by this control. 0b1111 The specified instructions are implemented. RO 51 49 51:49 Reserved, RES0. F64F64 48 48 48 Indicates support for the following SME instructions that accumulate into double-precision floating-point elements in the ZA array: The variants of the FMOPA and FMOPS instructions that accumulate into double-precision tiles. When FEAT_SME2 is implemented, the variants of the FADD, FMLA, FMLS, and FSUB instructions that accumulate into double-precision elements in ZA array vectors. FEAT_SME_F64F64 implements the functionality identified by the value 1. 0b0 The specified instructions are not implemented by this control. 0b1 The specified instructions are implemented . RO I16I32 47 44 3:0 Indicates support for SME2 SMOPA (2-way), SMOPS (2-way), UMOPA (2-way), and UMOPS (2-way) instructions that accumulate 16-bit outer products into 32-bit integer tiles. All other values are reserved. If FEAT_SME2 is implemented, the value 0b0000 is not permitted. 0b0000 The specified instructions are not implemented by this control. 0b0101 The specified instructions are implemented. RO When FEAT_SME2 is implemented 47 44 47:44 Reserved, RES0. Otherwise B16B16 43 43 43 Indicates support for the SME ZA-targeting non-widening BFloat16 BFADD, BFMLA, BFMLS, BFMOPA, BFMOPS, and BFSUB instructions with BFloat16 operands and results. FEAT_SME_B16B16 implements the functionality identified by the value 1. 0b0 The specified instructions are not implemented by this control. 0b1 The specified instructions are implemented. RO F16F16 42 42 42 Indicates support for the following SME2 half-precision floating-point instructions: FMOPA and FMOPS instructions that accumulate half-precision outer-products into half-precision tiles. Multi-vector FADD, FMLA, FMLS, and FSUB instructions with half-precision operands and results. Multi-vector FCVT and FCVTL instructions that convert half-precision inputs to single-precision results. FEAT_SME_F16F16 implements the functionality identified by the value 1. 0b0 The specified instructions are not implemented by this control. 0b1 The specified instructions are implemented. RO F8F16 41 41 41 Indicates support for the following SME2 instructions: The ZA-targeting FP8 instructions FDOT (2-way), FMLAL, FMOPA (2-way), and FVDOT that accumulate into half-precision floating-point elements. ZA-targeting non-widening half-precision FADD and FSUB instructions. FEAT_SME_F8F16 implements the functionality identified by the value 1. 0b0 The specified instructions are not implemented by this control. 0b1 The specified instructions are implemented. RO F8F32 40 40 40 Indicates support for the SME2 ZA-targeting FP8 FDOT (4-way), FMLALL, FMOPA (4-way), FVDOTB, and FVDOTT instructions that accumulate into single-precision floating-point elements. FEAT_SME_F8F32 implements the functionality identified by the value 1. 0b0 The specified instructions are not implemented by this control. 0b1 The specified instructions are implemented. RO I8I32 39 36 3:0 Indicates support for SME SMOPA, SMOPS, SUMOPA, SUMOPS, UMOPA, UMOPS, USMOPA, and USMOPS instructions that accumulate 8-bit outer products into 32-bit tiles All other values are reserved. If FEAT_SME is implemented, the value 0b0000 is not permitted. 0b0000 The specified instructions are not implemented by this control. 0b1111 The specified instructions are implemented. RO When FEAT_SME is implemented 39 36 39:36 Reserved, RES0. Otherwise F16F32 35 35 0 Indicates support for SME FMOPA and FMOPS instructions that accumulate half-precision floating-point outer products into single-precision floating-point tiles. If FEAT_SME is implemented, the value 0 is not permitted. 0b0 The specified instructions are not implemented by this control. 0b1 The specified instructions are implemented. RO When FEAT_SME is implemented 35 35 35 Reserved, RES0. Otherwise B16F32 34 34 0 Indicates support for SME BFMOPA and BFMOPS instructions that accumulate BFloat16 outer products into single-precision floating-point tiles. If FEAT_SME is implemented, the value 0 is not permitted. 0b0 The specified instructions are not implemented by this control. 0b1 The specified instructions are implemented. RO When FEAT_SME is implemented 34 34 34 Reserved, RES0. Otherwise BI32I32 33 33 0 Indicates support for SME BMOPA and BMOPS instructions that accumulate thirty-two 1-bit binary outer products into 32-bit integer tiles. If FEAT_SME2 is implemented, the value 0 is not permitted. 0b0 The specified instructions are not implemented by this control. 0b1 The specified instructions are implemented. RO When FEAT_SME2 is implemented 33 33 33 Reserved, RES0. Otherwise F32F32 32 32 0 Indicates support for SME FMOPA and FMOPS instructions that accumulate single-precision floating-point outer products into single-precision floating-point tiles. If FEAT_SME is implemented, the value 0 is not permitted. 0b0 The specified instructions are not implemented by this control. 0b1 The specified instructions are implemented. RO When FEAT_SME is implemented 32 32 32 Reserved, RES0. Otherwise 31 31 31 Reserved, RES0. SF8FMA 30 30 30 Indicates support for the SVE2 FP8 to single-precision and half-precision multiply-accumulate FMLALB, FMLALT, FMLALLBB, FMLALLBT, FMLALLTB, and FMLALLTT instructions when the PE is in Streaming SVE mode. Other features may support some of the specified instructions in Non-streaming SVE mode.If FEAT_SME2 and FEAT_FP8FMA are implemented, the value 0 is not permitted. FEAT_SSVE_FP8FMA implements the functionality identified by the value 1. 0b0 This control has no effect on Streaming SVE mode behavior. 0b1 The specified instructions are supported in Streaming SVE mode. RO SF8DP4 29 29 29 Indicates support for the SVE2 FP8 to single-precision 4-way dot product FDOT (4-way) instructions when the PE is in Streaming SVE mode. Other features may support some of the specified instructions in Non-streaming SVE mode.If FEAT_SME2 and FEAT_FP8DOT4 are implemented, the value 0 is not permitted. FEAT_SSVE_FP8DOT4 implements the functionality identified by the value 1. 0b0 This control has no effect on Streaming SVE mode behavior. 0b1 The specified instructions are supported in Streaming SVE mode. RO SF8DP2 28 28 28 Indicates support for the SVE2 FP8 to half-precision 2-way dot product FDOT (2-way) instructions when the PE is in Streaming SVE mode. Other features may support some of the specified instructions in Non-streaming SVE mode.If FEAT_SME2 and FEAT_FP8DOT2 are implemented, the value 0 is not permitted. FEAT_SSVE_FP8DOT2 implements the functionality identified by the value 1. 0b0 This control has no effect on Streaming SVE mode behavior. 0b1 The specified instructions are supported in Streaming SVE mode. RO 27 26 27:26 Reserved, RES0. SBitPerm 25 25 25 Indicates support for the SVE bit permute instructions identified as implemented by ID_AA64ZFR0_EL1.BitPerm, when the PE is in Streaming SVE mode. Other features may support some of the specified instructions in Non-streaming SVE mode. FEAT_SSVE_BitPerm implements the functionality identified by the value 1. 0b0 This control has no effect on Streaming SVE mode behavior. 0b1 The specified instructions are implemented when the PE is in Streaming SVE mode. RO AES 24 24 24 Indicates support for the SVE AES and 128-bit polynomial multiply long instructions identified as implemented by ID_AA64ZFR0_EL1.AES, when the PE is in Streaming SVE mode. Other features may support some of the specified instructions in Non-streaming SVE mode. FEAT_SSVE_AES implements the functionality identified by the value 1. 0b0 This control has no effect on Streaming SVE mode behavior. 0b1 The specified instructions are supported when the PE is in Streaming SVE mode. RO SFEXPA 23 23 23 Indicates support for the SVE FEXPA instruction when the PE is in Streaming SVE mode. Other features may support some of the specified instructions in Non-streaming SVE mode. FEAT_SSVE_FEXPA implements the functionality identified by the value 1. 0b0 This control has no effect on Streaming SVE mode behavior. 0b1 The specified instruction is supported when the PE is in Streaming SVE mode. RO 22 17 22:17 Reserved, RES0. STMOP 16 16 16 Indicates support for the following SME Structured sparsity outer product instructions: BFTMOPA (non-widening), if FEAT_SME_B16B16 is implemented. BFTMOPA (widening, BF16 to FP32). FTMOPA (non-widening, FP16), if FEAT_SME_F16F16 is implemented. FTMOPA (non-widening, FP32). FTMOPA (widening, 2-way, FP16 to FP32). FTMOPA (widening, 2-way, FP8 to FP16), if FEAT_SME_F8F16 is implemented. FTMOPA (widening, 4-way, FP8 to FP32) if FEAT_SME_F8F32 is implemented. STMOPA, SUTMOPA, USTMOPA, UTMOPA (4-way, Int8 to Int32). STMOPA, UTMOPA (2-way, Int16 to Int32). FEAT_SME_TMOP implements the functionality identified by the value 1. 0b0 The specified instructions are not implemented by this control. 0b1 The specified instructions are implemented. RO 15 1 15:1 Reserved, RES0. SMOP4 0 0 0 Indicates support for the following SME Quarter-tile outer product instructions: BFMOP4A, BFMOP4S (non-widening, BF16), if FEAT_SME_B16B16 is implemented. BFMOP4A, BFMOP4S (widening, 2-way, BF16 to FP32). FMOP4A, FMOP4S (non-widening, FP16), if FEAT_SME_F16F16 is implemented. FMOP4A, FMOP4S (non-widening, FP32). FMOP4A, FMOP4S (non-widening, FP64), if FEAT_SME_F64F64 is implemented. FMOP4A, FMOP4S (widening, 2-way, FP16 to FP32). FMOP4A(widening, 2-way, FP8 to FP16), if FEAT_SME_F8F16 is implemented. FMOP4A(widening, 4-way, FP8 to FP32) instruction, if FEAT_SME_F8F32 is implemented. SMOP4A, SMOP4S, SUMOP4A, SUMOP4S, UMOP4A, UMOP4S, USMOP4A, USMOP4S (4-way, Int8 to Int32). SMOP4A, SMOP4S, SUMOP4A, SUMOP4S, UMOP4A, UMOP4S, USMOP4A, USMOP4S (4-way, Int16 to Int64), if FEAT_SME_I16I64 is implemented. SMOP4A, SMOP4S, UMOP4A, UMOP4S (2-way, Int16 to Int32). FEAT_SME_MOP4 implements the functionality identified by the value 1. 0b0 The specified instructions are not implemented by this control. 0b1 The specified instructions are implemented. RO This register is read-only and can be accessed from EL1 and higher. This register is only accessible from the AArch64 state. MRS <Xt>, ID_AA64SMFR0_EL1 if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_AA64SMFR0_EL1()) || ImpDefBool("ID_AA64SMFR0_EL1 trapped by HCR_EL2.TID3")) && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64SMFR0_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64SMFR0_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_AA64SMFR0_EL1(); end; 2026-03-26 20:27:25 2026-03_rel