ID_AA64ZFR0_EL1 SVE Feature ID Register 0 Provides additional information about the implemented features of the AArch64 Scalable Vector Extension instruction set, when FEAT_SVE or FEAT_SME is implemented. For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'. Identification Registers Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.If FEAT_SME is implemented and FEAT_SVE is not implemented, then SVE instructions can only be executed when the PE is in Streaming SVE mode and the instructions are legal for execution in Streaming SVE mode. ID_AA64ZFR0_EL1 is a 64-bit register. 63 60 63:60 Reserved, RES0. F64MM 59 56 59:56 Indicates support for the SVE double-precision floating-point matrix multiply-accumulate instruction FMMLA, the LD1RO* instructions, the 128-bit element variants of the SVE TRN1, TRN2, UZP1, UZP2, ZIP1, and ZIP2 instructions. All other values are reserved. FEAT_F64MM implements the functionality identified by 0b0001. The instructions described by nonzero values of this field might not be legal when the PE is in Streaming SVE mode. 0b0000 This field does not indicate support for the specified instructions. 0b0001 The specified instructions are implemented. RO F32MM 55 52 55:52 Indicates support for the SVE single-precision floating-point matrix multiply-accumulate instruction FMMLA. All other values are reserved. FEAT_F32MM implements the functionality identified by 0b0001. The instructions described by nonzero values of this field might not be legal when the PE is in Streaming SVE mode. 0b0000 This field does not indicate support for the specified instruction. 0b0001 The specified instruction is implemented. RO F16MM 51 48 51:48 Indicates support for the SVE half-precision floating-point matrix multiply-accumulate to single-precision instruction FMMLA (widening, FP16 to FP32). FEAT_SVE_F16F32MM implements the functionality identified by 0b0001. The instructions described by nonzero values of this field might not be legal when the PE is in Streaming SVE mode. 0b0000 This field does not indicate support for the specified instruction. 0b0001 The specified instruction is implemented. RO I8MM 47 44 47:44 Indicates support for the following SVE 8-bit integer sum-of-products and accumulate to 32-bit integer instructions SMMLA, SUDOT, UMMLA, USMMLA, and USDOT. All other values are reserved. FEAT_I8MM implements the functionality identified by 0b0001. When Advanced SIMD and SVE are both implemented, this field must return the same value as ID_AA64ISAR1_EL1.I8MM. From Armv8.6, if SVE is implemented, the value 0b0000 is not permitted. SVE SMMLA, UMMLA, and USMMLA instructions might not be legal when the PE is in Streaming SVE mode. 0b0000 This field does not indicate support for the specified instructions. 0b0001 The specified instructions are implemented. RO SM4 43 40 43:40 Indicates support for SVE SM4 instructions. All other values are reserved. FEAT_SVE_SM4 implements the functionality identified by 0b0001. The instructions described by nonzero values of this field might not be legal when the PE is in Streaming SVE mode. 0b0000 This field does not indicate support for the specified instructions. 0b0001 SVE SM4E and SM4EKEY instructions are implemented. RO 39 36 39:36 Reserved, RES0. SHA3 35 32 35:32 Indicates support for the SVE SHA3 instructions. All other values are reserved. FEAT_SVE_SHA3 implements the functionality identified by 0b0001. If FEAT_SME2p1 is not implemented, then the instructions described by nonzero values of this field might not be legal when the PE is in Streaming SVE mode. 0b0000 This field does not indicate support for the specified instructions. 0b0001 SVE RAX1 instruction is implemented. RO 31 28 31:28 Reserved, RES0. B16B16 27 24 27:24 Indicates support for SVE non-widening BFloat16 instructions and SME multi-vector Z-targeting non-widening BFloat16 instructions. FEAT_SVE_B16B16 implements the functionality identified by 0b0001. FEAT_SVE_BFSCALE implements the functionality identified by 0b0010. 0b0000 This field does not indicate support for the specified instructions. 0b0001 The following non-widening BFloat16 instructions are implemented: SVE instructions: BFADD, BFCLAMP, BFMAX, BFMAXNM, BFMIN, BFMINNM, BFMLA, BFMLS, BFMUL, and BFSUB. If FEAT_SME2 is implemented, SME multi-vector Z-targeting instructions: BFCLAMP, BFMAX, BFMAXNM, BFMIN, and BFMINNM. 0b0010 As 0b0001, and adds the following non-widening BFloat16 instructions: SVE instruction BFSCALE. If FEAT_SME2 is implemented, SME multi-vector Z-targeting instructions BFMUL and BFSCALE. RO BF16 23 20 23:20 Indicates support for SVE BFloat16 instructions. All other values are reserved. FEAT_BF16 implements the functionality identified by 0b0001. FEAT_EBF16 implements the functionality identified by 0b0010. This field must return the same value as ID_AA64ISAR1_EL1.BF16. SVE BFMMLA instructions might not be legal when the PE is in Streaming SVE mode. From Armv8.6 and Armv9.1, the value 0b0000 is not permitted. 0b0000 SVE BFloat16 instructions are not implemented. 0b0001 SVE BFCVT, BFCVTNT, BFDOT, BFMLALB, BFMLALT, and BFMMLA instructions are implemented. 0b0010 As 0b0001, but the FPCR.EBF field is also supported. RO BitPerm 19 16 19:16 Indicates support for the SVE bit permute instructions BDEP, BEXT, and BGRP. All other values are reserved. FEAT_SVE_BitPerm implements the functionality identified by 0b0001 when the PE is not in Streaming SVE mode. FEAT_SSVE_BitPerm which is identified in ID_AA64SMFR0_EL1.SBitPerm, indicates whether the FEAT_SVE_BitPerm functionality is implemented when the PE is in Streaming SVE mode. 0b0000 This field does not indicate support for the specified instructions. 0b0001 The specified instructions are implemented. RO EltPerm 15 12 3:0 If FEAT_SVE2p2 is implemented, the following SVE instructions are implemented when the PE is not in Streaming SVE mode: 8-bit and 16-bit element COMPACT. 8-bit, 16-bit, 32-bit, and 64-bit element EXPAND. If FEAT_SME2p2 is implemented, the following SVE instructions are implemented when the PE is in Streaming SVE mode: 8-bit, 16-bit, 32-bit, and 64-bit element COMPACT and EXPAND. If FEAT_SVE2p2 or FEAT_SME2p2 is implemented, the value 0b0000 is not permitted. 0b0000 This field does not indicate support for the specified instructions. 0b0001 The specified instructions are implemented. RO When FEAT_SVE2p2 is implemented or FEAT_SME2p2 is implemented 15 12 15:12 Reserved, RES0. Otherwise 11 8 11:8 Reserved, RES0. AES 7 4 7:4 Indicates support for SVE Advanced Encryption Standard instructions and 128-bit polynomial multiply long instructions. All other values are reserved. FEAT_SVE_AES implements the functionality identified by the value 0b0001. FEAT_SVE_PMULL128 implements the functionality identified by the value 0b0010. FEAT_SVE_AES2 implements the functionality identified by 0b0011. If FEAT_SSVE_AES is not implemented, then the instructions described by nonzero values of this field might not be legal when the PE is in Streaming SVE mode. 0b0000 This field does not indicate support for the specified instructions. 0b0001 The following instructions are implemented: SVE single-vector AESD, AESE, AESIMC, and AESMC instructions. The 128-bit destination element variant of the SVE single-vector PMULLB and PMULLT instructions. 0b0010 As 0b0001. 0b0011 As 0b0010, and adds the following SVE instructions: Multi-vector AESD, AESDIMC, AESE and AESEMC instructions. Multi-vector 128-bit destination element PMULL and PMLAL instructions. RO SVEver 3 0 3:0 Indicates support for SVE instructions. All other values are reserved. FEAT_SVE2 implements the functionality identified by 0b0001 when the PE is not in Streaming SVE mode. FEAT_SME implements the functionality identified by 0b0001 when the PE is in Streaming SVE mode. FEAT_SME2p1 implements the functionality identified by 0b0010 when the PE is in Streaming SVE mode. FEAT_SVE2p1 implements the functionality identified by 0b0010 when the PE is not in Streaming SVE mode. FEAT_SVE2p2 implements the functionality identified by 0b0011 when the PE is not in Streaming SVE mode. FEAT_SME2p2 implements the functionality identified by 0b0011 when the PE is in Streaming SVE mode. From Armv9, the value 0b0000 is not permitted. From Armv9.4, the value 0b0001 is not permitted. From Armv9.6, the value 0b0010 is not permitted. 0b0000 The SVE instructions are implemented. 0b0001 As 0b0000, and adds the mandatory SVE2 instructions. 0b0010 As 0b0001, and adds the mandatory SVE2.1 instructions. 0b0011 As 0b0010, and adds the mandatory SVE2.2 instructions. RO When FEAT_SVE is implemented or FEAT_SME is implemented 3 0 3:0 Reserved, RES0. Otherwise MRS <Xt>, ID_AA64ZFR0_EL1 if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_AA64ZFR0_EL1()) || ImpDefBool("ID_AA64ZFR0_EL1 trapped by HCR_EL2.TID3")) && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64ZFR0_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_AA64ZFR0_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_AA64ZFR0_EL1(); end; 2026-03-26 20:27:25 2026-03_rel