ID_DFR1_EL1 AArch32 Debug Feature Register 1 when FEAT_AA64 is implemented ID_DFR1 Architectural AArch32 31 0 31 0 31 0 31 0 Provides top-level information about the debug system in AArch32. For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'. Identification Registers Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3. ID_DFR1_EL1 is a 64-bit register. When FEAT_AA32 is implemented ID_DFR1_EL1 63 8 63:8 Reserved, RES0. HPMN0 7 4 7:4 Zero PMU event counters for a Guest operating system. All other values are reserved. If FEAT_PMUv3 is not implemented, FEAT_FGT is not implemented, or EL2 is not implemented, the only permitted value is 0b0000. FEAT_HPMN0 implements the functionality identified by the value 0b0001. From Armv8.8, in an implementation that includes FEAT_PMUv3, FEAT_FGT, and EL2, the value 0b0000 is not permitted. 0b0000 Setting HDCR.HPMN to zero has CONSTRAINED UNPREDICTABLE behavior. 0b0001 Setting HDCR.HPMN to zero has defined behavior. RO MTPMU 3 0 3:0 Multi-threaded PMU extension. All other values are reserved. FEAT_MTPMU implements the functionality identified by the value 0b0001. From Armv8.6, in an implementation that includes FEAT_PMUv3, the value 0b0000 is not permitted. In an implementation that does not include FEAT_PMUv3, the value 0b0001 is not permitted. 0b0000 FEAT_MTPMU not implemented. If FEAT_PMUv3 is implemented, it is IMPLEMENTATION DEFINED whether PMEVTYPER<n>.MT are read/write or RES0. 0b0001 FEAT_MTPMU and FEAT_PMUv3 implemented. PMEVTYPER<n>.MT are read/write. When FEAT_MTPMU is disabled, the Effective values of PMEVTYPER<n>.MT are 0. 0b1111 FEAT_MTPMU not implemented. If FEAT_PMUv3 is implemented, PMEVTYPER<n>.MT are RES0. RO 63 0 63:0 Reserved, UNKNOWN. When FEAT_AA32 is implemented MRS <Xt>, ID_DFR1_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_DFR1_EL1()) || ImpDefBool("ID_DFR1_EL1 trapped by HCR_EL2.TID3")) && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_DFR1_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_DFR1_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_DFR1_EL1(); end; 2026-03-26 20:27:25 2026-03_rel