ID_ISAR3_EL1 AArch32 Instruction Set Attribute Register 3 when FEAT_AA64 is implemented ID_ISAR3 Architectural AArch32 31 0 31 0 31 0 31 0 Provides information about the instruction sets implemented by the PE in AArch32 state. Must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR4_EL1, and ID_ISAR5_EL1. For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'. Identification Registers ID_ISAR3_EL1 is a 64-bit register. When FEAT_AA32 is implemented 63 32 63:32 Reserved, RES0. T32EE 31 28 31:28 Indicates the implemented T32EE instructions. All other values are reserved. In Armv8-A, the only permitted value is 0b0000. 0b0000 None implemented. 0b0001 Adds the ENTERX and LEAVEX instructions, and modifies the load behavior to include null checking. RO TrueNOP 27 24 27:24 Indicates the implemented true NOP instructions. All other values are reserved. In Armv8-A, the only permitted value is 0b0001. 0b0000 None implemented. This means there are no NOP instructions that do not have any register dependencies. 0b0001 Adds true NOP instructions in both the T32 and A32 instruction sets. This also permits additional NOP-compatible hints. RO T32Copy 23 20 23:20 Indicates the support for T32 non flag-setting MOV instructions. All other values are reserved. In Armv8-A, the only permitted value is 0b0001. 0b0000 Not supported. This means that in the T32 instruction set, encoding T1 of the MOV (register) instruction does not support a copy from a low register to a low register. 0b0001 Adds support for T32 instruction set encoding T1 of the MOV (register) instruction, copying from a low register to a low register. RO TabBranch 19 16 19:16 Indicates the implemented Table Branch instructions in the T32 instruction set. All other values are reserved. In Armv8-A, the only permitted value is 0b0001. 0b0000 None implemented. 0b0001 Adds the TBB and TBH instructions. RO SynchPrim 15 12 15:12 Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate the implemented Synchronization Primitive instructions. All other combinations of SynchPrim and SynchPrim_frac are reserved. In Armv8-A, the only permitted value is 0b0010. 0b0000 If SynchPrim_frac == 0b0000, no Synchronization Primitives implemented. 0b0001 If SynchPrim_frac == 0b0000, adds the LDREX and STREX instructions. If SynchPrim_frac == 0b0011, also adds the CLREX, LDREXB, STREXB, and STREXH instructions. 0b0010 If SynchPrim_frac == 0b0000, as for [0b0001, 0b0011] and also adds the LDREXD and STREXD instructions. RO SVC 11 8 11:8 Indicates the implemented SVC instructions. All other values are reserved. In Armv8-A, the only permitted value is 0b0001. 0b0000 Not implemented. 0b0001 Adds the SVC instruction. RO SIMD 7 4 7:4 Indicates the implemented SIMD instructions. All other values are reserved. In Armv8-A, the only permitted value is 0b0011. The SIMD field relates only to implemented instructions that perform SIMD operations on the general-purpose registers. In an implementation that supports Advanced SIMD and floating-point instructions, MVFR0, MVFR1, and MVFR2 give information about the implemented Advanced SIMD instructions. 0b0000 None implemented. 0b0001 Adds the SSAT and USAT instructions, and the Q bit in the PSRs. 0b0011 As for 0b0001, and adds the PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, and UXTB16 instructions. Also adds support for the GE[3:0] bits in the PSRs. RO Saturate 3 0 3:0 Indicates the implemented Saturate instructions. All other values are reserved. In Armv8-A, the only permitted value is 0b0001. 0b0000 None implemented. This means no non-Advanced SIMD saturate instructions are implemented. 0b0001 Adds the QADD, QDADD, QDSUB, and QSUB instructions, and the Q bit in the PSRs. RO 63 0 63:0 Reserved, UNKNOWN. When FEAT_AA32 is implemented MRS <Xt>, ID_ISAR3_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_ISAR3_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_ISAR3_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_ISAR3_EL1(); end; 2026-03-26 20:27:25 2026-03_rel