ID_ISAR4_EL1 AArch32 Instruction Set Attribute Register 4 when FEAT_AA64 is implemented ID_ISAR4 Architectural AArch32 31 0 31 0 31 0 31 0 Provides information about the instruction sets implemented by the PE in AArch32 state. Must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, and ID_ISAR5_EL1. For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'. Identification Registers ID_ISAR4_EL1 is a 64-bit register. When FEAT_AA32 is implemented 63 32 63:32 Reserved, RES0. SWP_frac 31 28 31:28 Indicates support for the memory system locking the bus for SWP or SWPB instructions. All other values are reserved. This field is valid only if ID_ISAR0.Swap is 0b0000. In Armv8-A, the only permitted value is 0b0000. 0b0000 SWP or SWPB instructions not implemented. 0b0001 SWP or SWPB implemented but only in a uniprocessor context. SWP and SWPB do not guarantee whether memory accesses from other Requesters can come between the load memory access and the store memory access of the SWP or SWPB. RO PSR_M 27 24 27:24 Indicates the implemented M-profile instructions to modify the PSRs. All other values are reserved. In Armv8-A, the only permitted value is 0b0000. 0b0000 None implemented. 0b0001 Adds the M-profile forms of the CPS, MRS, and MSR instructions. RO SynchPrim_frac 23 20 23:20 Used in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions. All other combinations of SynchPrim and SynchPrim_frac are reserved. In Armv8-A, the only permitted value is 0b0000. 0b0000 If SynchPrim == 0b0000, no Synchronization Primitives implemented. If SynchPrim == 0b0001, adds the LDREX and STREX instructions. If SynchPrim == 0b0010, also adds the CLREX, LDREXB, LDREXH, STREXB, STREXH, LDREXD, and STREXD instructions. 0b0011 If SynchPrim == 0b0001, adds the LDREX, STREX, CLREX, LDREXB, LDREXH, STREXB, and STREXH instructions. RO Barrier 19 16 19:16 Indicates the implemented Barrier instructions in the T32 and A32 instruction sets. All other values are reserved. In Armv8-A, the only permitted value is 0b0001. 0b0000 None implemented. Barrier operations are provided only as System instructions in the (coproc==0b1111) encoding space. 0b0001 Adds the DMB, DSB, and ISB barrier instructions. RO SMC 15 12 15:12 Indicates the implemented SMC instructions. All other values are reserved. In Armv8-A, the permitted values are: If EL3 is implemented and EL1 can use AArch32, the only permitted value is 0b0001. If neither EL3 nor EL2 is implemented, the only permitted value is 0b0000. If EL1 cannot use AArch32, this field has the value 0b0000. 0b0000 None implemented. 0b0001 Adds the SMC instruction. RO Writeback 11 8 11:8 Indicates the support for Writeback addressing modes. All other values are reserved. In Armv8-A, the only permitted value is 0b0001. 0b0000 Basic support. Only the LDM, STM, PUSH, POP, SRS, and RFE instructions support writeback addressing modes. These instructions support all of their writeback addressing modes. 0b0001 Adds support for all of the writeback addressing modes. RO WithShifts 7 4 7:4 Indicates the support for instructions with shifts. All other values are reserved. In Armv8-A, the only permitted value is 0b0100. 0b0000 Nonzero shifts supported only in MOV and shift instructions. 0b0001 Adds support for shifts of loads and stores over the range LSL 0-3. 0b0011 As for 0b0001, and adds support for other constant shift options, both on load/store and other instructions. 0b0100 As for 0b0011, and adds support for register-controlled shift options. RO Unpriv 3 0 3:0 Indicates the implemented unprivileged instructions. All other values are reserved. In Armv8-A, the only permitted value is 0b0010. 0b0000 None implemented. No T variant instructions are implemented. 0b0001 Adds the LDRBT, LDRT, STRBT, and STRT instructions. 0b0010 As for 0b0001, and adds the LDRHT, LDRSBT, LDRSHT, and STRHT instructions. RO 63 0 63:0 Reserved, UNKNOWN. When FEAT_AA32 is implemented MRS <Xt>, ID_ISAR4_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_ISAR4_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_ISAR4_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_ISAR4_EL1(); end; 2026-03-26 20:27:25 2026-03_rel