ID_MMFR0_EL1 AArch32 Memory Model Feature Register 0 when FEAT_AA64 is implemented ID_MMFR0 Architectural AArch32 31 0 31 0 31 0 31 0 Provides information about the implemented memory model and memory management support in AArch32 state. For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'. Identification Registers ID_MMFR0_EL1 is a 64-bit register. When FEAT_AA32 is implemented 63 32 63:32 Reserved, RES0. InnerShr 31 28 31:28 Innermost Shareability. Indicates the innermost shareability domain implemented. All other values are reserved. From Armv8 the permitted values are 0b0000, 0b0001, and 0b1111. This field is valid only if the implementation supports two levels of shareability, as indicated by ID_MMFR0_EL1.ShareLvl having the value 0b0001. When ID_MMFR0_EL1.ShareLvl is zero, this field is UNKNOWN. 0b0000 Implemented as Non-cacheable. 0b0001 Implemented with hardware coherency support. 0b1111 Shareability ignored. RO FCSE 27 24 27:24 Indicates whether the implementation includes the FCSE. All other values are reserved. From Armv8 the only permitted value is 0b0000. 0b0000 Not supported. 0b0001 Support for FCSE. RO AuxReg 23 20 23:20 Auxiliary Registers. Indicates support for Auxiliary registers. All other values are reserved. From Armv8 the only permitted value is 0b0010. Accesses to unimplemented Auxiliary registers are UNDEFINED. 0b0000 None supported. 0b0001 Support for Auxiliary Control Register only. 0b0010 Support for Auxiliary Fault Status Registers (AIFSR and ADFSR) and Auxiliary Control Register. RO TCM 19 16 19:16 Indicates support for TCMs and associated DMAs. All other values are reserved. In Armv8-A the only permitted value is 0b0000. 0b0000 Not supported. 0b0001 Support is IMPLEMENTATION DEFINED. 0b0010 Support for TCM only, Armv6 implementation. 0b0011 Support for TCM and DMA, Armv6 implementation. RO ShareLvl 15 12 15:12 Shareability Levels. Indicates the number of shareability levels implemented. All other values are reserved. From Armv8 the only permitted value is 0b0001. 0b0000 One level of shareability implemented. 0b0001 Two levels of shareability implemented. RO OuterShr 11 8 11:8 Outermost Shareability. Indicates the outermost shareability domain implemented. All other values are reserved. From Armv8 the permitted values are 0b0000, 0b0001, and 0b1111. 0b0000 Implemented as Non-cacheable. 0b0001 Implemented with hardware coherency support. 0b1111 Shareability ignored. RO PMSA 7 4 7:4 Indicates support for a PMSA. All other values are reserved. In Armv8-A the only permitted value is 0b0000. 0b0000 Not supported. 0b0001 Support for IMPLEMENTATION DEFINED PMSA. 0b0010 Support for PMSAv6, with a Cache Type Register implemented. 0b0011 Support for PMSAv7, with support for memory subsections. Armv7-R profile. RO VMSA 3 0 3:0 Indicates support for a VMSA. All other values are reserved. In Armv8-A the only permitted value is 0b0101. 0b0000 Not supported. 0b0001 Support for IMPLEMENTATION DEFINED VMSA. 0b0010 Support for VMSAv6, with Cache and TLB Type Registers implemented. 0b0011 Support for VMSAv7, with support for remapping and the Access flag. Armv7-A profile. 0b0100 As for 0b0011, and adds support for the PXN bit in the Short-descriptor translation table format descriptors. 0b0101 As for 0b0100, and adds support for the Long-descriptor translation table format. RO 63 0 63:0 Reserved, UNKNOWN. When FEAT_AA32 is implemented MRS <Xt>, ID_MMFR0_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_MMFR0_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_MMFR0_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_MMFR0_EL1(); end; 2026-03-26 20:27:25 2026-03_rel