ID_MMFR1_EL1 AArch32 Memory Model Feature Register 1 when FEAT_AA64 is implemented ID_MMFR1 Architectural AArch32 31 0 31 0 31 0 31 0 Provides information about the implemented memory model and memory management support in AArch32 state. For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'. Identification Registers ID_MMFR1_EL1 is a 64-bit register. When FEAT_AA32 is implemented 63 32 63:32 Reserved, RES0. BPred 31 28 31:28 Branch Predictor. Indicates branch predictor management requirements. All other values are reserved. In Armv8-A, the permitted values are 0b0010, 0b0011, and 0b0100. For values other than 0b0000 and 0b0100 the Arm Architecture Reference Manual, or the product documentation, might give more information about the required maintenance. 0b0000 No branch predictor, or no MMU present. Implies a fixed MPU configuration. 0b0001 Branch predictor requires flushing on: Enabling or disabling a stage of address translation. Writing new data to instruction locations. Writing new mappings to the translation tables. Changes to the TTBR0, TTBR1, or TTBCR registers. Changes to the ContextID or ASID, or to the FCSE ProcessID if this is supported. 0b0010 Branch predictor requires flushing on: Enabling or disabling a stage of address translation. Writing new data to instruction locations. Writing new mappings to the translation tables. Any change to the TTBR0, TTBR1, or TTBCR registers without a change to the corresponding ContextID or ASID, or FCSE ProcessID if this is supported. 0b0011 Branch predictor requires flushing only on writing new data to instruction locations. 0b0100 For execution correctness, branch predictor requires no flushing at any time. RO L1TstCln 27 24 27:24 Level 1 cache Test and Clean. Indicates the supported Level 1 data cache test and clean operations, for Harvard or unified cache implementations. All other values are reserved. In Armv8-A, the only permitted value is 0b0000. 0b0000 None supported. 0b0001 Supported Level 1 data cache test and clean operations are: Test and clean data cache. 0b0010 As for 0b0001, and adds: Test, clean, and invalidate data cache. RO L1Uni 23 20 23:20 Level 1 Unified cache. Indicates the supported entire Level 1 cache maintenance operations for a unified cache implementation. All other values are reserved. In Armv8-A, the only permitted value is 0b0000. 0b0000 None supported. 0b0001 Supported entire Level 1 cache operations are: Invalidate cache, including branch predictor if appropriate. Invalidate branch predictor, if appropriate. 0b0010 As for 0b0001, and adds: Clean cache, using a recursive model that uses the cache dirty status bit. Clean and invalidate cache, using a recursive model that uses the cache dirty status bit. RO L1Hvd 19 16 19:16 Level 1 Harvard cache. Indicates the supported entire Level 1 cache maintenance operations for a Harvard cache implementation. All other values are reserved. In Armv8-A, the only permitted value is 0b0000. 0b0000 None supported. 0b0001 Supported entire Level 1 cache operations are: Invalidate instruction cache, including branch predictor if appropriate. Invalidate branch predictor, if appropriate. 0b0010 As for 0b0001, and adds: Invalidate data cache. Invalidate data cache and instruction cache, including branch predictor if appropriate. 0b0011 As for 0b0010, and adds: Clean data cache, using a recursive model that uses the cache dirty status bit. Clean and invalidate data cache, using a recursive model that uses the cache dirty status bit. RO L1UniSW 15 12 15:12 Level 1 Unified cache by Set/Way. Indicates the supported Level 1 cache line maintenance operations by set/way, for a unified cache implementation. All other values are reserved. In Armv8-A, the only permitted value is 0b0000. 0b0000 None supported. 0b0001 Supported Level 1 unified cache line maintenance operations by set/way are: Clean cache line by set/way. 0b0010 As for 0b0001, and adds: Clean and invalidate cache line by set/way. 0b0011 As for 0b0010, and adds: Invalidate cache line by set/way. RO L1HvdSW 11 8 11:8 Level 1 Harvard cache by Set/Way. Indicates the supported Level 1 cache line maintenance operations by set/way, for a Harvard cache implementation. All other values are reserved. In Armv8-A, the only permitted value is 0b0000. 0b0000 None supported. 0b0001 Supported Level 1 Harvard cache line maintenance operations by set/way are: Clean data cache line by set/way. Clean and invalidate data cache line by set/way. 0b0010 As for 0b0001, and adds: Invalidate data cache line by set/way. 0b0011 As for 0b0010, and adds: Invalidate instruction cache line by set/way. RO L1UniVA 7 4 7:4 Level 1 Unified cache by Virtual Address. Indicates the supported Level 1 cache line maintenance operations by VA, for a unified cache implementation. All other values are reserved. In Armv8-A, the only permitted value is 0b0000. 0b0000 None supported. 0b0001 Supported Level 1 unified cache line maintenance operations by VA are: Clean cache line by VA. Invalidate cache line by VA. Clean and invalidate cache line by VA. 0b0010 As for 0b0001, and adds: Invalidate branch predictor by VA, if branch predictor is implemented. RO L1HvdVA 3 0 3:0 Level 1 Harvard cache by Virtual Address. Indicates the supported Level 1 cache line maintenance operations by VA, for a Harvard cache implementation. All other values are reserved. In Armv8-A, the only permitted value is 0b0000. 0b0000 None supported. 0b0001 Supported Level 1 Harvard cache line maintenance operations by VA are: Clean data cache line by VA. Invalidate data cache line by VA. Clean and invalidate data cache line by VA. Clean instruction cache line by VA. 0b0010 As for 0b0001, and adds: Invalidate branch predictor by VA, if branch predictor is implemented. RO 63 0 63:0 Reserved, UNKNOWN. When FEAT_AA32 is implemented MRS <Xt>, ID_MMFR1_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_MMFR1_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_MMFR1_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_MMFR1_EL1(); end; 2026-03-26 20:27:25 2026-03_rel