ID_MMFR5_EL1 AArch32 Memory Model Feature Register 5 when FEAT_AA64 is implemented ID_MMFR5 Architectural AArch32 31 0 31 0 31 0 31 0 Provides information about the implemented memory model and memory management support in AArch32 state. For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'. Identification Registers Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3. ID_MMFR5_EL1 is a 64-bit register. When FEAT_AA32 is implemented 63 8 63:8 Reserved, RES0. nTLBPA 7 4 7:4 Indicates support for intermediate caching of translation table walks. Non-coherent physical translation caches are non-coherent caches of previous valid translation table entries since the last completed relevant TLBI applicable to the PE, where either: The caching is indexed by the physical address of the location holding the translation table entry. The caching is used for stage 1 translations and is indexed by the intermediate physical address of the location holding the translation table entry. All other values are reserved. FEAT_nTLBPA implements the functionality identified by the value 0b0001. From Armv8.0, the permitted values are 0b0000 and 0b0001. 0b0000 The intermediate caching of translation table walks might include non-coherent physical translation caches. 0b0001 The intermediate caching of translation table walks does not include non-coherent physical translation caches. RO ETS 3 0 3:0 Indicates support for Enhanced Translation Synchronization. All other values are reserved. FEAT_ETS2 implements the functionality identified by the value 0b0010. FEAT_ETS3 implements the functionality identified by the value 0b0011. From Armv8.8, the values 0b0000 and 0b0001 are not permitted. From Armv9.5, the value 0b0010 is not permitted. 0b0000 Enhanced Translation Synchronization is not supported. 0b0001 Enhanced Translation Synchronization is not supported. 0b0010 FEAT_ETS2 is implemented. 0b0011 FEAT_ETS3 is implemented. RO 63 0 63:0 Reserved, UNKNOWN. When FEAT_AA32 is implemented MRS <Xt>, ID_MMFR5_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_MMFR5_EL1()) || ImpDefBool("ID_MMFR5_EL1 trapped by HCR_EL2.TID3")) && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_MMFR5_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_MMFR5_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_MMFR5_EL1(); end; 2026-03-26 20:27:25 2026-03_rel