ID_PFR1_EL1 AArch32 Processor Feature Register 1 when FEAT_AA64 is implemented ID_PFR1 Architectural AArch32 31 0 31 0 31 0 31 0 Gives information about the AArch32 programmers' model. Must be interpreted with ID_PFR0_EL1. For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'. Identification Registers ID_PFR1_EL1 is a 64-bit register. When FEAT_AA32 is implemented 63 32 63:32 Reserved, RES0. GIC 31 28 31:28 System register GIC CPU interface. All other values are reserved. 0b0000 GIC CPU interface system registers not implemented. 0b0001 System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. 0b0011 System register interface to version 4.1 of the GIC CPU interface is supported. RO Virt_frac 27 24 27:24 Virtualization fractional field. When the Virtualization field is 0b0000, determines the support for Virtualization Extensions. All other values are reserved. In Armv8-A, the permitted values are: 0b0000 when EL2 is implemented. 0b0001 when EL2 is not implemented. This field is valid only when the value of ID_PFR1_EL1.Virtualization is 0, otherwise it holds the value 0b0000. The ID_ISAR registers do not identify whether the instructions added by the Virtualization Extensions are implemented. 0b0000 No Virtualization Extensions are implemented. 0b0001 The following Virtualization Extensions are implemented: The SCR.SIF bit, if EL3 is implemented. The modifications to the SCR.AW and SCR.FW bits described in the Virtualization Extensions, if EL3 is implemented. The MSR (banked register) and MRS (banked register) instructions. The ERET instruction. RO Sec_frac 23 20 23:20 Security fractional field. When the Security field is 0b0000, determines the support for Security Extensions. All other values are reserved. In Armv8-A, the permitted values are: 0b0000 when EL3 is implemented. 0b0001 or 0b0010 when EL3 is not implemented. This field is valid only when the value of ID_PFR1_EL1.Security is 0, otherwise it holds the value 0b0000. 0b0000 No Security Extensions are implemented. 0b0001 The following Security Extensions are implemented: The VBAR register. The TTBCR.PD0 and TTBCR.PD1 bits. 0b0010 As for 0b0001, plus the ability to access Secure or Non-secure physical memory is supported. RO GenTimer 19 16 19:16 Generic Timer support. All other values are reserved. FEAT_ECV implements the functionality identified by the value 0b0010. In Armv8.0, the only permitted value is 0b0001. From Armv8.6, the only permitted value is 0b0010. 0b0000 Generic Timer is not implemented. 0b0001 Generic Timer is implemented. 0b0010 Generic Timer is implemented, and also includes support for CNTHCTL.EVNTIS and CNTKCTL.EVNTIS fields, and CNTPCTSS and CNTVCTSS counter views. RO Virtualization 15 12 15:12 Virtualization support. All other values are reserved. In Armv8-A, the permitted values are: 0b0000 when EL2 is not implemented. 0b0001 when EL2 is implemented. In an implementation that includes EL2, if EL2 cannot use AArch32 but EL1 can use AArch32, then this field has the value 0b0001. If EL1 cannot use AArch32, then this field has the value 0b0000. The ID_ISARs do not identify whether the HVC instruction is implemented. 0b0000 EL2, Hyp mode, and the HVC instruction not implemented. 0b0001 EL2, Hyp mode, the HVC instruction, and all the features described by Virt_frac == 0b0001 implemented. RO MProgMod 11 8 11:8 M-profile programmers' model support. All other values are reserved. In Armv8-A the only permitted value is 0b0000. 0b0000 Not supported. 0b0010 Support for two-stack programmers' model. RO Security 7 4 7:4 Security support. All other values are reserved. In Armv8-A, the permitted values are: 0b0000 when EL3 is not implemented. 0b0001 when EL3 is implemented. In an implementation that includes EL3, if EL3 cannot use AArch32 but EL1 can use AArch32, then this field has the value 0b0001. If EL1 cannot use AArch32, then this field has the value 0b0000. 0b0000 EL3, Monitor mode, and the SMC instruction not implemented. 0b0001 EL3, Monitor mode, the SMC instruction, and all the features described by Sec_frac == 0b0001 implemented. 0b0010 As for 0b0001, and adds the ability to set the NSACR.RFR bit. Not permitted in Armv8 as the NSACR.RFR bit is RES0. RO ProgMod 3 0 3:0 Support for the standard programmers' model for Armv4 and later. Model must support User, FIQ, IRQ, Supervisor, Abort, Undefined, and System modes. All other values are reserved. In Armv8-A, the permitted values are 0b0001 and 0b0000. If EL1 cannot use AArch32, then this field has the value 0b0000. 0b0000 Not supported. 0b0001 Supported. RO 63 0 63:0 Reserved, UNKNOWN. When FEAT_AA32 is implemented MRS <Xt>, ID_PFR1_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_PFR1_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_PFR1_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_PFR1_EL1(); end; 2026-03-26 20:27:25 2026-03_rel