ID_PFR2_EL1 AArch32 Processor Feature Register 2 when FEAT_AA64 is implemented ID_PFR2 Architectural AArch32 31 0 31 0 31 0 31 0 Gives information about the AArch32 programmers' model. Must be interpreted with ID_PFR0_EL1 and ID_PFR1_EL1. For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'. Identification Registers Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3. ID_PFR2_EL1 is a 64-bit register. When FEAT_AA32 is implemented 63 12 63:12 Reserved, RES0. RAS_frac 11 8 11:8 RAS Extension fractional field. All other values are reserved. FEAT_RAS implements the functionality identified by the value 0b0000. When ERRIDR_EL1.NUM is zero, this field is permitted to have the value 0b0000, regardless of whether FEAT_RASv1p1 is implemented. When ERRIDR_EL1.NUM is nonzero, FEAT_RASv1p1 implements the functionality identified by the value 0b0001. This field is valid only if ID_PFR0_EL1.RAS == 0b0001. 0b0000 If ID_PFR0_EL1.RAS == 0b0001, Support for the Reliability, Availability, and Serviceability Extension is implemented. 0b0001 If ID_PFR0_EL1.RAS == 0b0001, as 0b0000 and adds support for additional ERXMISC<m> System registers. Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to ERR<n>STATUS and support for the optional RAS Timestamp Extension. RO SSBS 7 4 7:4 Speculative Store Bypassing controls in AArch64 state. In Armv8.0, the permitted values are 0b0000 and 0b0001. From Armv8.5, the only permitted value is 0b0001. All other values are reserved. 0b0000 AArch32 provides no mechanism to control the use of Speculative Store Bypassing. 0b0001 AArch32 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe. RO CSV3 3 0 3:0 Speculative use of faulting data. All other values are reserved. FEAT_CSV3 implements the functionality identified by the value 0b0001. In Armv8.0, the permitted values are 0b0000 and 0b0001. From Armv8.5, the only permitted value is 0b0001. If FEAT_E0PD is implemented, FEAT_CSV3 must be implemented. 0b0000 This PE does not disclose whether data loaded under speculation with a permission or domain fault can be used to form an address or generate condition codes or SVE predicate values to be used by other instructions in the speculative sequence. 0b0001 Data loaded under speculation with a permission or domain fault cannot be used to form an address, generate condition codes, or generate SVE predicate values to be used by other instructions in the speculative sequence. The execution timing of any other instructions in the speculative sequence is not a function of the data loaded under speculation. RO 63 0 63:0 Reserved, UNKNOWN. When FEAT_AA32 is implemented MRS <Xt>, ID_PFR2_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_PFR2_EL1()) || ImpDefBool("ID_PFR2_EL1 trapped by HCR_EL2.TID3")) && HCR_EL2().TID3 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_PFR2_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ID_PFR2_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ID_PFR2_EL1(); end; 2026-03-26 20:27:25 2026-03_rel