IFSR32_EL2 Instruction Fault Status Register (EL2) when FEAT_AA32EL1 is implemented and FEAT_AA64 is implemented IFSR Architectural AArch32 31 0 31 0 31 0 31 0 Allows access to the AArch32 IFSR register from AArch64 state only. Its value has no effect on execution in AArch64 state. Exception If EL2 is not implemented but EL3 is implemented, and EL1 is capable of using AArch32, then this register is not RES0. IFSR32_EL2 is a 64-bit register. When TTBCR.EAE == '0' TTBCR.EAE==0 63 17 63:17 Reserved, RES0. FnV 16 16 16 FAR not Valid, for a synchronous External abort other than a synchronous External abort on a translation table walk. This field is valid only for a synchronous External abort other than a synchronous External abort on a translation table walk. It is RES0 for all other Prefetch Abort exceptions. 0b0 IFAR is valid. 0b1 IFAR is not valid, and holds an UNKNOWN value. AU 15 13 15:13 Reserved, RES0. ExT 12 12 12 External abort type. This bit can be used to provide an IMPLEMENTATION DEFINED classification of External aborts. In an implementation that does not provide any classification of External aborts, this bit is RES0. For aborts other than External aborts this bit always returns 0. AU 11 11 11 Reserved, RES0. FS 10 10 10, 3:0 Fault Status bits. Bits [10] and [3:0] are interpreted together. All other values are reserved. For more information about the lookup level associated with a fault, see 'The level associated with MMU faults on a Short-descriptor translation table lookup'. The FS field is split as follows: FS[4] is IFSR32_EL2[10]. FS[3:0] is IFSR32_EL2[3:0]. 10 10 3 0 FS 0b00001 PC alignment fault. 0b00010 Debug exception. 0b00011 Access flag fault, level 1. 0b00101 Translation fault, level 1. 0b00110 Access flag fault, level 2. 0b00111 Translation fault, level 2. 0b01000 Synchronous External abort, not on translation table walk. 0b01001 Domain fault, level 1. 0b01011 Domain fault, level 2. 0b01100 Synchronous External abort, on translation table walk, level 1. 0b01101 Permission fault, level 1. 0b01110 Synchronous External abort, on translation table walk, level 2. 0b01111 Permission fault, level 2. 0b10000 TLB conflict abort. 0b10100 IMPLEMENTATION DEFINED fault (Lockdown fault). 0b11001 Synchronous parity or ECC error on memory access, not on translation table walk. When FEAT_RAS is not implemented 0b11100 Synchronous parity or ECC error on translation table walk, level 1. When FEAT_RAS is not implemented 0b11110 Synchronous parity or ECC error on translation table walk, level 2. When FEAT_RAS is not implemented AU LPAE 9 9 9 On taking a Data Abort exception, this bit is set as follows: Hardware does not interpret this bit to determine the behavior of the memory system, and therefore software can set this bit to 0 or 1 without affecting operation. 0b0 Using the Short-descriptor translation table formats. 0b1 Using the Long-descriptor translation table formats. AU 8 4 8:4 Reserved, RES0. FS[3:0] 3 0 10, 3:0 This field is bits[3:0] of FS[4:0]. See FS[4] for the field description. When TTBCR.EAE == '1' TTBCR.EAE==1 63 17 63:17 Reserved, RES0. FnV 16 16 16 FAR not Valid, for a synchronous External abort other than a synchronous External abort on a translation table walk. This field is valid only for a synchronous External abort other than a synchronous External abort on a translation table walk. It is RES0 for all other Prefetch Abort exceptions. 0b0 IFAR is valid. 0b1 IFAR is not valid, and holds an UNKNOWN value. AU 15 13 15:13 Reserved, RES0. ExT 12 12 12 External abort type. This bit can be used to provide an IMPLEMENTATION DEFINED classification of External aborts. In an implementation that does not provide any classification of External aborts, this bit is RES0. For aborts other than External aborts this bit always returns 0. AU 11 10 11:10 Reserved, RES0. LPAE 9 9 9 On taking a Data Abort exception, this bit is set as follows: Hardware does not interpret this bit to determine the behavior of the memory system, and therefore software can set this bit to 0 or 1 without affecting operation. 0b0 Using the Short-descriptor translation table formats. 0b1 Using the Long-descriptor translation table formats. AU 8 6 8:6 Reserved, RES0. STATUS 5 0 5:0 Fault status bits. Possible values of this field are: All other values are reserved. When FEAT_RAS is implemented, 0b011000, 0b011101, 0b011110, and 0b011111 are reserved. For more information about the lookup level associated with a fault, see 'The level associated with MMU faults on a Long-descriptor translation table lookup'. 0b000000 Address size fault in translation table base register. 0b000001 Address size fault, level 1. 0b000010 Address size fault, level 2. 0b000011 Address size fault, level 3. 0b000101 Translation fault, level 1. 0b000110 Translation fault, level 2. 0b000111 Translation fault, level 3. 0b001001 Access flag fault, level 1. 0b001010 Access flag fault, level 2. 0b001011 Access flag fault, level 3. 0b001101 Permission fault, level 1. 0b001110 Permission fault, level 2. 0b001111 Permission fault, level 3. 0b010000 Synchronous External abort, not on translation table walk. 0b010101 Synchronous External abort on translation table walk, level 1. 0b010110 Synchronous External abort on translation table walk, level 2. 0b010111 Synchronous External abort on translation table walk, level 3. 0b011000 Synchronous parity or ECC error on memory access, not on translation table walk. When FEAT_RAS is not implemented 0b011101 Synchronous parity or ECC error on memory access on translation table walk, level 1. When FEAT_RAS is not implemented 0b011110 Synchronous parity or ECC error on memory access on translation table walk, level 2. When FEAT_RAS is not implemented 0b011111 Synchronous parity or ECC error on memory access on translation table walk, level 3. When FEAT_RAS is not implemented 0b100001 PC alignment fault. 0b100010 Debug exception. 0b110000 TLB conflict abort. AU When TTBCR.EAE == '0' When TTBCR.EAE == '1' MRS <Xt>, IFSR32_EL2 if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = IFSR32_EL2(); elsif PSTATE.EL == EL3 then X{64}(t) = IFSR32_EL2(); end; MSR IFSR32_EL2, <Xt> if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then IFSR32_EL2() = X{64}(t); elsif PSTATE.EL == EL3 then IFSR32_EL2() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel