ISR_EL1
Interrupt Status Register
when FEAT_AA64 is implemented
ISR
Architectural
AArch32
31
0
31
0
31
0
31
0
Shows the pending status of IRQ and FIQ interrupts and SError exceptions.
When FEAT_NMI is implemented, also shows whether a pending IRQ or FIQ interrupt has Superpriority.
Exception
ISR_EL1 is a 64-bit register.
63
11
63:11
Reserved, RES0.
IS
10
10
0
IRQ with Superpriority pending bit. Indicates whether an IRQ interrupt with Superpriority is pending.
If all of the following apply, then this field shows the pending status of virtual IRQ interrupts with Superpriority:
EL2 is implemented and enabled in the current Security state.
HCR_EL2.IMO is 1.
The PE is executing at EL1.
Otherwise, this field shows the pending status of physical IRQ interrupts with Superpriority.
0b0
No pending IRQ with Superpriority.
0b1
An IRQ interrupt with Superpriority is pending.
When FEAT_NMI is implemented
10
10
10
Reserved, RES0.
Otherwise
FS
9
9
0
FIQ with Superpriority pending bit. Indicates whether an FIQ interrupt with Superpriority is pending.
If all of the following apply, then this field shows the pending status of virtual FIQ interrupts with Superpriority:
EL2 is implemented and enabled in the current Security state.
HCR_EL2.FMO is 1.
The PE is executing at EL1.
Otherwise, this field shows the pending status of physical FIQ interrupts with Superpriority.
0b0
No pending FIQ with Superpriority.
0b1
An FIQ interrupt with Superpriority is pending.
When FEAT_NMI is implemented
9
9
9
Reserved, RES0.
Otherwise
A
8
8
8
SError exception pending bit. Indicates whether an SError exception is pending.
If all of the following apply, then this field shows the pending status of virtual SError exceptions:
EL2 is implemented and enabled in the current Security state.
Any of the following apply:
HCR_EL2.AMO is 1.
FEAT_DoubleFault2 is implemented and the Effective value of HCRX_EL2.TMEA is 1.
The PE is executing at EL1.
Otherwise, if all of the following apply, then this field shows the pending status of delegated SError exceptions:
FEAT_E3DSE is implemented.
SCR_EL3.EnDSE is 1.
The PE is executing at EL2 or EL1.
Otherwise, this field shows the pending status of physical SError exceptions.
If the physical SError exception is edge-triggered, this field is cleared to zero when the physical SError exception is taken.
0b0
No pending SError.
0b1
An SError exception is pending.
I
7
7
7
IRQ pending bit. Indicates whether an IRQ interrupt is pending.
If all of the following apply, then this field shows the pending status of virtual IRQ interrupts:
EL2 is implemented and enabled in the current Security state.
HCR_EL2.IMO is 1.
The PE is executing at EL1.
Otherwise, this field shows the pending status of physical IRQ interrupts.
This bit indicates the presence of a pending IRQ interrupt regardless of whether the interrupt has Superpriority.
0b0
No pending IRQ.
0b1
An IRQ interrupt is pending.
F
6
6
6
FIQ pending bit. Indicates whether an FIQ interrupt is pending.
If all of the following apply, then this field shows the pending status of virtual FIQ interrupts:
EL2 is implemented and enabled in the current Security state.
HCR_EL2.FMO is 1.
The PE is executing at EL1.
Otherwise, this field shows the pending status of physical FIQ interrupts.
This bit indicates the presence of a pending FIQ interrupt regardless of whether the interrupt has Superpriority.
0b0
No pending FIQ.
0b1
An FIQ interrupt is pending.
5
0
5:0
Reserved, RES0.
MRS <Xt>, ISR_EL1
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().ISR_EL1 == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
else
X{64}(t) = ISR_EL1();
end;
elsif PSTATE.EL == EL2 then
X{64}(t) = ISR_EL1();
elsif PSTATE.EL == EL3 then
X{64}(t) = ISR_EL1();
end;
2026-03-26 20:27:25
2026-03_rel