LORC_EL1 LORegion Control (EL1) when FEAT_LOR is implemented and FEAT_AA64 is implemented Enables and disables LORegions, and selects the current LORegion descriptor. Memory If no LORegion descriptors are supported by the PE, then this register is RES0. LORC_EL1 is a 64-bit register. 63 10 63:10 Reserved, RES0. DS 9 2 9:2 Descriptor Select. Selects the current LORegion descriptor accessed by LORSA_EL1, LOREA_EL1, and LORN_EL1. If this field points to an LORegion descriptor that is not supported by an implementation, then the registers LORN_EL1, LOREA_EL1, and LORSA_EL1 are RES0. The number of LORegion descriptors in IMPLEMENTATION DEFINED. The maximum number of LORegion descriptors supported is 256. If the number is less than 256, then bits[63:M+2] are RES0, where M is Log₂(Number of LORegion descriptors supported by the implementation). AU 1 1 1 Reserved, RES0. EN 0 0 0 Enable. Indicates whether LORegions are enabled. This bit is permitted to be cached in a TLB. 0b0 Disabled. Memory accesses do not match any LORegions. 0b1 Enabled. Memory accesses may match a LORegion. '0' MRS <Xt>, LORC_EL1 if !(IsFeatureImplemented(FEAT_LOR) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TLOR == '1' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().NS == '0' then Undefined(); elsif EL2Enabled() && HCR_EL2().TLOR == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().LORC_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().TLOR == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = LORC_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().NS == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TLOR == '1' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().TLOR == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = LORC_EL1(); end; elsif PSTATE.EL == EL3 then if SCR_EL3().NS == '0' then Undefined(); else X{64}(t) = LORC_EL1(); end; end; MSR LORC_EL1, <Xt> if !(IsFeatureImplemented(FEAT_LOR) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TLOR == '1' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().NS == '0' then Undefined(); elsif EL2Enabled() && HCR_EL2().TLOR == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().LORC_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().TLOR == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else LORC_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().NS == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TLOR == '1' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().TLOR == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else LORC_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if SCR_EL3().NS == '0' then Undefined(); else LORC_EL1() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel