<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>LORSA_EL1</reg_short_name>
        
        <reg_long_name>LORegion Start Address (EL1)</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_LOR is implemented and FEAT_AA64 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Indicates whether the current LORegion descriptor selected by <register_link state="AArch64" id="AArch64-lorc_el1.xml">LORC_EL1</register_link>.DS is enabled, and holds the physical address of the start of the LORegion.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
            <reg_group>Memory</reg_group>
      </reg_groups>
      <reg_configuration>
        
    
      <configuration_text>
        <para>This register is <arm-defined-word>RES0</arm-defined-word> if any of the following apply:</para>

      </configuration_text>
      <configuration_text>
        <list type="unordered">
<listitem><content>No LORegion descriptors are supported by the PE.</content>
</listitem><listitem><content><register_link state="AArch64" id="AArch64-lorc_el1.xml">LORC_EL1</register_link>.DS points to a LORegion that is not supported by the PE.</content>
</listitem></list>
      </configuration_text>

      </reg_configuration>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>LORSA_EL1 is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields>
    <para>Any of the fields in this register are permitted to be cached in a TLB.</para>
  </text_before_fields>
  <field id="fieldset_0-63_56" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>63</field_msb>
    <field_lsb>56</field_lsb>
    <rel_range>63:56</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-55_16" has_partial_fieldset="True" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>SA</field_name>
    <field_msb>55</field_msb>
    <field_lsb>16</field_lsb>
    <rel_range>55:16</rel_range>
    <field_description order="before"/>
    <partial_fieldset>
      <fields id="fieldset_0-55_16_0" length="40">
        <fields_condition>When FEAT_D128 is implemented</fields_condition>
        <text_before_fields/>
        <field id="fieldset_0-55_16_0-39_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
          <field_name>SA</field_name>
          <field_msb>39</field_msb>
          <field_lsb>0</field_lsb>
          <rel_range>39:0</rel_range>
          <field_description order="before"><para>Bits [55:16] of the start physical address of the LORegion described in the current LORegion descriptor selected by <register_link state="AArch64" id="AArch64-lorc_el1.xml">LORC_EL1</register_link>.DS.</para>
<para>Bits[15:0] of this address are <hexnumber>0x0000</hexnumber>.</para>
<para>For implementations with fewer than 56 physical address bits, the corresponding upper bits of this field are <arm-defined-word>RES0</arm-defined-word>.</para></field_description>
          <field_resets>
            <field_reset reset_type="Warm">
              <field_reset_standard_text>AU</field_reset_standard_text>
            </field_reset>
          </field_resets>
        </field>
        <text_after_fields/>
      </fields>
      <reg_fieldset length="40">
        <fields_condition>When FEAT_D128 is implemented</fields_condition>
        <fieldat id="fieldset_0-55_16_0-39_0" msb="39" lsb="0"/>
      </reg_fieldset>
    </partial_fieldset>
    <partial_fieldset>
      <fields id="fieldset_0-55_16_1" length="40">
        <fields_condition>When FEAT_LPA is implemented and FEAT_D128 is not implemented</fields_condition>
        <text_before_fields/>
        <field id="fieldset_0-55_16_1-39_36" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
          <field_msb>39</field_msb>
          <field_lsb>36</field_lsb>
          <rel_range>39:36</rel_range>
          <field_description order="before"/>
          <field_description order="before">
            <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
          </field_description>
        </field>
        <field id="fieldset_0-55_16_1-35_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
          <field_name>SA</field_name>
          <field_msb>35</field_msb>
          <field_lsb>0</field_lsb>
          <rel_range>35:0</rel_range>
          <field_description order="before"><para>Bits [51:16] of the start physical address of the LORegion described in the current LORegion descriptor selected by <register_link state="AArch64" id="AArch64-lorc_el1.xml">LORC_EL1</register_link>.DS.</para>
<para>Bits[15:0] of this address are <hexnumber>0x0000</hexnumber>.</para>
<para>For implementations with fewer than 52 physical address bits, the corresponding upper bits of this field are <arm-defined-word>RES0</arm-defined-word>.</para></field_description>
          <field_resets>
            <field_reset reset_type="Warm">
              <field_reset_standard_text>AU</field_reset_standard_text>
            </field_reset>
          </field_resets>
        </field>
        <text_after_fields/>
      </fields>
      <reg_fieldset length="40">
        <fields_condition>When FEAT_LPA is implemented and FEAT_D128 is not implemented</fields_condition>
        <fieldat id="fieldset_0-55_16_1-39_36" msb="39" lsb="36"/>
        <fieldat id="fieldset_0-55_16_1-35_0" msb="35" lsb="0"/>
      </reg_fieldset>
    </partial_fieldset>
    <partial_fieldset>
      <fields id="fieldset_0-55_16_2" length="40">
        <fields_condition>When FEAT_LPA is not implemented</fields_condition>
        <text_before_fields/>
        <field id="fieldset_0-55_16_2-39_32" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
          <field_msb>39</field_msb>
          <field_lsb>32</field_lsb>
          <rel_range>39:32</rel_range>
          <field_description order="before"/>
          <field_description order="before">
            <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
          </field_description>
        </field>
        <field id="fieldset_0-55_16_2-31_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
          <field_name>SA</field_name>
          <field_msb>31</field_msb>
          <field_lsb>0</field_lsb>
          <rel_range>31:0</rel_range>
          <field_description order="before"><para>Bits [47:16] of the start physical address of the LORegion described in the current LORegion descriptor selected by <register_link state="AArch64" id="AArch64-lorc_el1.xml">LORC_EL1</register_link>.DS.</para>
<para>Bits[15:0] of this address are <hexnumber>0x0000</hexnumber>.</para>
<para>For implementations with fewer than 48 physical address bits, the corresponding upper bits of this field are <arm-defined-word>RES0</arm-defined-word>.</para></field_description>
          <field_resets>
            <field_reset reset_type="Warm">
              <field_reset_standard_text>AU</field_reset_standard_text>
            </field_reset>
          </field_resets>
        </field>
        <text_after_fields/>
      </fields>
      <reg_fieldset length="40">
        <fields_condition>When FEAT_LPA is not implemented</fields_condition>
        <fieldat id="fieldset_0-55_16_2-39_32" msb="39" lsb="32"/>
        <fieldat id="fieldset_0-55_16_2-31_0" msb="31" lsb="0"/>
      </reg_fieldset>
    </partial_fieldset>
  </field>
  <field id="fieldset_0-15_1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>15</field_msb>
    <field_lsb>1</field_lsb>
    <rel_range>15:1</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-0_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>Valid</field_name>
    <field_msb>0</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>0</rel_range>
    <field_description order="before">
      <para>Indicates whether the current LORegion descriptor is enabled.</para>
    </field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>LORegion descriptor is disabled.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>LORegion descriptor is enabled.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_number>'0'</field_reset_number>
      </field_reset>
    </field_resets>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_56" msb="63" lsb="56"/>
  <fieldat id="fieldset_0-55_16" msb="55" lsb="16"/>
  <fieldat id="fieldset_0-15_1" msb="15" lsb="1"/>
  <fieldat id="fieldset_0-0_0" msb="0" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          






    
        
        <access_mechanism accessor="MRS LORSA_EL1" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, LORSA_EL1</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b000"/>
                
                <enc n="CRn" v="0b1010"/>
                
                <enc n="CRm" v="0b0100"/>
                
                <enc n="op2" v="0b000"/>
            </encoding>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !(IsFeatureImplemented(FEAT_LOR) &amp;&amp; IsFeatureImplemented(FEAT_AA64)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SCR_EL3().TLOR == '1' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; SCR_EL3().NS == '0' then
        Undefined();
    elsif EL2Enabled() &amp;&amp; HCR_EL2().TLOR == '1' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT) &amp;&amp; (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') &amp;&amp; HFGRTR_EL2().LORSA_EL1 == '1' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; SCR_EL3().TLOR == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = LORSA_EL1();
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; SCR_EL3().NS == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SCR_EL3().TLOR == '1' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; SCR_EL3().TLOR == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = LORSA_EL1();
    end;
elsif PSTATE.EL == EL3 then
    if SCR_EL3().NS == '0' then
        Undefined();
    else
        X{64}(t) = LORSA_EL1();
    end;
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MSRregister LORSA_EL1" type="SystemAccessor">
            <encoding>
            <access_instruction>MSR LORSA_EL1, &lt;Xt&gt;</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b000"/>
                
                <enc n="CRn" v="0b1010"/>
                
                <enc n="CRm" v="0b0100"/>
                
                <enc n="op2" v="0b000"/>
            </encoding>
            <access_permission>
                <ps name="MSRregister" sections="1" secttype="access_permission">
                <pstext>
if !(IsFeatureImplemented(FEAT_LOR) &amp;&amp; IsFeatureImplemented(FEAT_AA64)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SCR_EL3().TLOR == '1' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; SCR_EL3().NS == '0' then
        Undefined();
    elsif EL2Enabled() &amp;&amp; HCR_EL2().TLOR == '1' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT) &amp;&amp; (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') &amp;&amp; HFGWTR_EL2().LORSA_EL1 == '1' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; SCR_EL3().TLOR == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        LORSA_EL1() = X{64}(t);
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; SCR_EL3().NS == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SCR_EL3().TLOR == '1' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; SCR_EL3().TLOR == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        LORSA_EL1() = X{64}(t);
    end;
elsif PSTATE.EL == EL3 then
    if SCR_EL3().NS == '0' then
        Undefined();
    else
        LORSA_EL1() = X{64}(t);
    end;
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>