MAIR_EL1
Memory Attribute Indirection Register (EL1)
when FEAT_AA64 is implemented
PRRR
Architectural
AArch32
31
0
31
0
31
0
31
0
when TTBCR.EAE == '0'
MAIR0
Architectural
AArch32
31
0
31
0
31
0
31
0
when TTBCR.EAE == '1'
NMRR
Architectural
AArch32
63
32
31
0
63
32
31
0
when TTBCR.EAE == '0'
MAIR1
Architectural
AArch32
63
32
31
0
63
32
31
0
when TTBCR.EAE == '1'
Provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations at EL1.
Memory
MAIR_EL1 is a 64-bit register.
MAIR_EL1 is permitted to be cached in a TLB.
Attr<n>
63
0
63:0
Memory Attribute encoding.
When FEAT_AIE is implemented and stage 1 Attributes Index Extension is enabled and AttrIndx[3] in a Long descriptor format translation table entry is 0, or when FEAT_AIE is not implemented, AttrIndx[2:0] gives the value of <n> in Attr<n>.
When FEAT_AIE is implemented and stage 1 Attributes Index Extension is enabled and AttrIndx[3] in a Long descriptor format translation table entry is 1, see MAIR2_EL1.Attr
Attr is encoded as follows:
AttrMeaning
0b0000dd00Device memory.
See encoding of 'dd' for the type of Device memory.
0b0000dd01If FEAT_XS is implemented:
Device memory with the XS attribute set to 0.
See encoding of 'dd' for the type of Device memory.
Otherwise,UNPREDICTABLE.
0b0000dd1xUNPREDICTABLE.
0booooiiiiwhere oooo != 0000
and iiii != 0000Normal memory. See encoding of 'oooo' and 'iiii' for the
type of Normal memory.
0b01000000If FEAT_XS is implemented:
Normal Inner Non-cacheable, Outer Non-cacheable memory
with the XS attribute set to 0.
Otherwise,UNPREDICTABLE.
0b10100000If FEAT_XS is implemented:
Normal Inner Write-through Cacheable, Outer Write-through Cacheable,
Read-Allocate, No-Write Allocate, Non-transient memory
with the XS attribute set to 0.
Otherwise,UNPREDICTABLE.
0b11110000If FEAT_MTE2 is implemented:
Tagged Normal Inner Write-Back, Outer Write-Back,
Read-Allocate, Write-Allocate Non-transient memory.
Otherwise,UNPREDICTABLE.
0bxxxx0000where xxxx != 0000
and xxxx != 0100
and xxxx != 1010
and xxxx != 1111UNPREDICTABLE.
dd is encoded as follows:
'dd'Meaning
0b00Device-nGnRnE memory.
0b01Device-nGnRE memory.
0b10Device-nGRE memory.
0b11Device-GRE memory.
oooo is encoded as follows:
'oooo'Meaning
0b0000See encoding of Attr.
0b00RWwhere RW != 00Normal memory, Outer Write-Through Transient.
0b0100Normal memory, Outer Non-cacheable.
0b01RWwhere RW != 00Normal memory, Outer Write-Back Transient.
0b10RWNormal memory, Outer Write-Through Non-transient.
0b11RWNormal memory, Outer Write-Back Non-transient.
R encodes the Outer Read-Allocate policy and W encodes the Outer Write-Allocate policy.
iiii is encoded as follows:
'iiii'Meaning
0b0000See encoding of Attr.
0b00RWwhere RW != 00Normal memory, Inner Write-Through Transient.
0b0100Normal memory, Inner Non-cacheable.
0b01RWwhere RW != 00Normal memory, Inner Write-Back Transient.
0b10RWNormal memory, Inner Write-Through Non-transient.
0b11RWNormal memory, Inner Write-Back Non-transient.
R encodes the Inner Read-Allocate policy and W encodes the Inner Write-Allocate policy.
In oooo and iiii, R and W are encoded as follows:
'R' or 'W'Meaning
0b0No Allocate.
0b1Allocate.
When FEAT_XS is implemented, stage 1 Inner Write-Back Cacheable, Outer Write-Back Cacheable memory types have the XS attribute set to 0.
7
0
AU
When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name MAIR_EL1 or MAIR_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name.
MRS <Xt>, MAIR_EL1
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2().TRVM == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().MAIR_EL1 == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EffectiveHCR_EL2_NVx() IN {'111'} then
X{64}(t) = NVMem(0x140);
else
X{64}(t) = MAIR_EL1();
end;
elsif PSTATE.EL == EL2 then
if ELIsInHost(EL2) then
X{64}(t) = MAIR_EL2();
else
X{64}(t) = MAIR_EL1();
end;
elsif PSTATE.EL == EL3 then
X{64}(t) = MAIR_EL1();
end;
MSR MAIR_EL1, <Xt>
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2().TVM == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().MAIR_EL1 == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EffectiveHCR_EL2_NVx() IN {'111'} then
NVMem(0x140) = X{64}(t);
else
MAIR_EL1() = X{64}(t);
end;
elsif PSTATE.EL == EL2 then
if ELIsInHost(EL2) then
MAIR_EL2() = X{64}(t);
else
MAIR_EL1() = X{64}(t);
end;
elsif PSTATE.EL == EL3 then
MAIR_EL1() = X{64}(t);
end;
MRS <Xt>, MAIR_EL12
When FEAT_VHE is implemented
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EffectiveHCR_EL2_NVx() == '101' then
X{64}(t) = NVMem(0x140);
elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then
AArch64_SystemAccessTrap(EL2, 0x18);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
if ELIsInHost(EL2) then
X{64}(t) = MAIR_EL1();
else
Undefined();
end;
elsif PSTATE.EL == EL3 then
if ELIsInHost(EL2) then
X{64}(t) = MAIR_EL1();
else
Undefined();
end;
end;
MSR MAIR_EL12, <Xt>
When FEAT_VHE is implemented
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EffectiveHCR_EL2_NVx() == '101' then
NVMem(0x140) = X{64}(t);
elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then
AArch64_SystemAccessTrap(EL2, 0x18);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
if ELIsInHost(EL2) then
MAIR_EL1() = X{64}(t);
else
Undefined();
end;
elsif PSTATE.EL == EL3 then
if ELIsInHost(EL2) then
MAIR_EL1() = X{64}(t);
else
Undefined();
end;
end;
2026-03-26 20:27:25
2026-03_rel