MDSCR_EL1
Monitor Debug System Control Register
when FEAT_AA64 is implemented
DBGDSCRext
Architectural
AArch32
31
0
31
0
31
0
31
0
DBGDSCRint
Architectural
AArch32
15
15
15
15
15
15
15
15
DBGDSCRint
Architectural
AArch32
12
12
12
12
12
12
12
12
DBGDSCRint
Architectural
AArch32
5
2
5
2
5
2
5
2
EDSCR
Architectural
External
31
6
31
6
31
29
27
26
23
21
19
19
14
14
6
6
31
29
27
26
23
21
19
19
14
14
6
6
EDSCR2
Architectural
External
35
33
3
1
35
35
33
33
3
3
1
1
Main control register for the debug implementation.
Debug
MDSCR_EL1 is a 64-bit register.
63
51
63:51
Reserved, RES0.
EnSTEPOP
50
50
0
Software step control bit. Enable execution from MDSTEPOP_EL1. Permitted values are:
0b0
Execution from MDSTEPOP_EL1 is disabled.
0b1
Execution from MDSTEPOP_EL1 is not disabled by this control.
AU
When FEAT_STEP2 is implemented
50
50
50
Reserved, RES0.
Otherwise
49
36
49:36
Reserved, RES0.
EHBWE
35
35
0
Extended Halting Breakpoint and Watchpoint Enable. Used for save/restore of EDSCR2.EHBWE.
When OSLSR_EL1.OSLK is 0, software must treat this field as UNK/SBZP.
When OSLSR_EL1.OSLK is 1, this field holds the value of EDSCR2.EHBWE. Reads and writes of this field are indirect accesses to EDSCR2.EHBWE.
It is IMPLEMENTATION DEFINED whether this field is implemented or is RES0 when 16 or fewer breakpoints are implemented, 16 or fewer watchpoints are implemented, and MDSELR_EL1 is implemented as RAZ/WI.
'0'
When OSLSR_EL1.OSLK == '0'
RO
RW
When FEAT_Debugv8p9 is implemented
35
35
35
Reserved, RES0.
Otherwise
EnSPM
34
34
0
Enable access to System PMU registers. When disabled, accesses to System PMU registers generate a trap to EL1.
In AArch64 state, the instructions affected by this control are: MRS and MSR accesses to SPMCNTENCLR_EL0, SPMCNTENSET_EL0, SPMCR_EL0, SPMEVCNTR<n>_EL0, SPMEVFILT2R<n>_EL0, SPMEVFILTR<n>_EL0, SPMEVTYPER<n>_EL0, SPMOVSCLR_EL0, SPMOVSSET_EL0, and SPMSELR_EL0.
Unless the instruction generates a higher priority exception:
If EL2 is implemented and enabled in the current Security state, and HCR_EL2.TGE is 1, then trapped instructions generate an exception to EL2.
Otherwise, trapped instructions generate an exception to EL1.
Trapped instructions are reported using EC syndrome value 0x18.
0b0
Accesses of the specified System PMU registers at EL0 are trapped to EL1, unless the instruction generates a higher priority exception.
0b1
Accesses of the specified System PMU registers are not trapped by this mechanism.
AU
When FEAT_SPMU is implemented
34
34
34
Reserved, RES0.
Otherwise
TTA
33
33
0
Trap Trace Accesses. Used for save/restore of EDSCR2.TTA.
When OSLSR_EL1.OSLK is 0, software must treat this field as UNK/SBZP.
When OSLSR_EL1.OSLK is 1, this field holds the value of EDSCR2.TTA. Reads and writes of this field are indirect accesses to EDSCR2.TTA.
'0'
When OSLSR_EL1.OSLK == '0'
RO
RW
When FEAT_TRBE_EXT is implemented or FEAT_ETEv1p3 is implemented
33
33
33
Reserved, RES0.
Otherwise
EMBWE
32
32
0
Extended Monitor Breakpoint and Watchpoint Enable. Enables use of additional breakpoints or watchpoints.
It is IMPLEMENTATION DEFINED whether this field is implemented or is RES0 when 16 or fewer breakpoints are implemented, 16 or fewer watchpoints are implemented, and MDSELR_EL1 is implemented as RAZ/WI.
This field is ignored by the PE and treated as zero when any of the following are true:
EL3 is implemented and MDCR_EL3.EBWE is 0.
EL2 is implemented and enabled in the current Security state, and MDCR_EL2.EBWE is 0.
0b0
Breakpoint and Watchpoint exceptions are disabled for each breakpoint <n> and watchpoint <n>, where n is greater than or equal to 16.
The Effective value of MDSELR_EL1.BANK is zero at EL1.
0b1
Breakpoint and Watchpoint exceptions are not affected by this mechanism.
The Effective value of MDSELR_EL1.BANK is not affected by this field.
'0'
AU
When FEAT_Debugv8p9 is implemented
32
32
32
Reserved, RES0.
Otherwise
TFO
31
31
0
Trace Filter override. Used for save/restore of EDSCR.TFO.
When OSLSR_EL1.OSLK == 0, software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this bit holds the value of EDSCR.TFO. Reads and writes of this bit are indirect accesses to EDSCR.TFO.
'0'
When OSLSR_EL1.OSLK == '1'
RW
When OSLSR_EL1.OSLK == '0'
RO
When FEAT_TRF is implemented
31
31
31
Reserved, RES0.
Otherwise
RXfull
30
30
30
Used for save/restore of EDSCR.RXfull.
When OSLSR_EL1.OSLK == 0, software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this bit holds the value of EDSCR.RXfull. Reads and writes of this bit are indirect accesses to EDSCR.RXfull.
'0'
When OSLSR_EL1.OSLK == '1'
RW
When OSLSR_EL1.OSLK == '0'
RO
TXfull
29
29
29
Used for save/restore of EDSCR.TXfull.
When OSLSR_EL1.OSLK == 0, software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this bit holds the value of EDSCR.TXfull. Reads and writes of this bit are indirect accesses to EDSCR.TXfull.
'0'
When OSLSR_EL1.OSLK == '1'
RW
When OSLSR_EL1.OSLK == '0'
RO
28
28
28
Reserved, RES0.
RXO
27
27
27
Used for save/restore of EDSCR.RXO.
When OSLSR_EL1.OSLK == 0, software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this bit holds the value of EDSCR.RXO. Reads and writes of this bit are indirect accesses to EDSCR.RXO.
When OSLSR_EL1.OSLK == 1, if bits [27,6] of the value written to MDSCR_EL1 are {1,0}, that is, the RXO bit is 1 and the ERR bit is 0, the PE sets EDSCR.{RXO,ERR} to UNKNOWN values.
'0'
When OSLSR_EL1.OSLK == '1'
RW
When OSLSR_EL1.OSLK == '0'
RO
TXU
26
26
26
Used for save/restore of EDSCR.TXU.
When OSLSR_EL1.OSLK == 0, software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this bit holds the value of EDSCR.TXU. Reads and writes of this bit are indirect accesses to EDSCR.TXU.
When OSLSR_EL1.OSLK == 1, if bits [26,6] of the value written to MDSCR_EL1 are {1,0}, that is, the TXU bit is 1 and the ERR bit is 0, the PE sets EDSCR.{TXU,ERR} to UNKNOWN values.
'0'
When OSLSR_EL1.OSLK == '1'
RW
When OSLSR_EL1.OSLK == '0'
RO
25
24
25:24
Reserved, RES0.
INTdis
23
22
23:22
Used for save/restore of EDSCR.INTdis.
When OSLSR_EL1.OSLK == 0, software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this field holds the value of EDSCR.INTdis. Reads and writes of this field are indirect accesses to EDSCR.INTdis.
'00'
When OSLSR_EL1.OSLK == '1'
RW
When OSLSR_EL1.OSLK == '0'
RO
TDA
21
21
21
Used for save/restore of EDSCR.TDA.
When OSLSR_EL1.OSLK == 0, software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this bit holds the value of EDSCR.TDA. Reads and writes of this bit are indirect accesses to EDSCR.TDA.
'0'
When OSLSR_EL1.OSLK == '1'
RW
When OSLSR_EL1.OSLK == '0'
RO
20
20
20
Reserved, RES0.
SC2
19
19
0
Used for save/restore of EDSCR.SC2.
When OSLSR_EL1.OSLK == 0, software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this bit holds the value of EDSCR.SC2. Reads and writes of this bit are indirect accesses to EDSCR.SC2.
'0'
When OSLSR_EL1.OSLK == '1'
RW
When OSLSR_EL1.OSLK == '0'
RO
When FEAT_PCSRv8 is implemented, FEAT_VHE is implemented, and FEAT_PCSRv8p2 is not implemented
19
19
19
Reserved, RES0.
Otherwise
18
16
18:16
Reserved, RAZ/WI.
Hardware must implement this field as RAZ/WI. Software must not rely on the register reading as zero, and must use a read-modify-write sequence to write to the register.
MDE
15
15
15
Monitor debug events. Enable Breakpoint, Watchpoint, and Vector Catch exceptions.
0b0
Breakpoint, Watchpoint, and Vector Catch exceptions disabled.
0b1
Breakpoint, Watchpoint, and Vector Catch exceptions enabled.
AU
HDE
14
14
14
Used for save/restore of EDSCR.HDE.
When OSLSR_EL1.OSLK == 0, software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this bit holds the value of EDSCR.HDE. Reads and writes of this bit are indirect accesses to EDSCR.HDE.
'0'
When OSLSR_EL1.OSLK == '1'
RW
When OSLSR_EL1.OSLK == '0'
RO
KDE
13
13
13
Local (kernel) debug enable. If ELD is using AArch64, enable debug exceptions within ELD. Permitted values are:
RES0 if ELD is using AArch32.
0b0
Debug exceptions, other than Breakpoint Instruction exceptions, disabled within ELD.
0b1
All debug exceptions enabled within ELD.
AU
TDCC
12
12
12
Traps EL0 accesses to the Debug Communication Channel (DCC) registers to EL1, or to EL2 when it is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, from both Execution states, as follows:
In AArch64 state, MRS or MSR accesses to the following DCC System registers are trapped, reported using EC syndrome value 0x18:
MDCCSR_EL0.
If not in Debug state, DBGDTR_EL0, DBGDTRTX_EL0, and DBGDTRRX_EL0.
In AArch32 state, MRC or MCR accesses to the following registers are trapped, reported using EC syndrome value 0x05.
DBGDSCRint, DBGDIDR, DBGDSAR, DBGDRAR.
If not in Debug state, DBGDTRRXint, and DBGDTRTXint.
In AArch32 state, LDC access to DBGDTRRXint and STC access to DBGDTRTXint are trapped, reported using EC syndrome value 0x06.
In AArch32 state, MRRC accesses to DBGDSAR and DBGDRAR are trapped, reported using EC syndrome value 0x0C.
0b0
This control does not cause any instructions to be trapped.
0b1
EL0 using AArch64: EL0 accesses to the AArch64 DCC System registers are trapped.
EL0 using AArch32: EL0 accesses to the AArch32 DCC System registers are trapped.
AU
11
7
11:7
Reserved, RES0.
ERR
6
6
6
Used for save/restore of EDSCR.ERR.
When OSLSR_EL1.OSLK == 0, software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this bit holds the value of EDSCR.ERR. Reads and writes of this bit are indirect accesses to EDSCR.ERR.
'0'
When OSLSR_EL1.OSLK == '1'
RW
When OSLSR_EL1.OSLK == '0'
RO
5
1
5:1
Reserved, RES0.
SS
0
0
0
Software step control bit. If ELD is using AArch64, enable Software step. Permitted values are:
RES0 if ELD is using AArch32.
0b0
Software step disabled
0b1
Software step enabled.
AU
MRS <Xt>, MDSCR_EL1
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDA == '1' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().MDSCR_EL1 == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && MDCR_EL2().[TDE,TDA] != '00' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif EffectiveHCR_EL2_NVx() IN {'1x1'} then
X{64}(t) = NVMem(0x158);
else
X{64}(t) = MDSCR_EL1();
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDA == '1' then
Undefined();
elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
X{64}(t) = MDSCR_EL1();
end;
elsif PSTATE.EL == EL3 then
X{64}(t) = MDSCR_EL1();
end;
MSR MDSCR_EL1, <Xt>
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDA == '1' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().MDSCR_EL1 == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && MDCR_EL2().[TDE,TDA] != '00' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif EffectiveHCR_EL2_NVx() IN {'1x1'} then
NVMem(0x158) = X{64}(t);
else
MDSCR_EL1() = X{64}(t);
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDA == '1' then
Undefined();
elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
MDSCR_EL1() = X{64}(t);
end;
elsif PSTATE.EL == EL3 then
MDSCR_EL1() = X{64}(t);
end;
2026-03-26 20:27:25
2026-03_rel