<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>MDSELR_EL1</reg_short_name>
        
        <reg_long_name>Breakpoint and Watchpoint Selection Register</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_Debugv8p9 is implemented and FEAT_AA64 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Selects the current breakpoints or watchpoints accessed by System register instructions.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>Unknown</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>MDSELR_EL1 is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_6" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>63</field_msb>
    <field_lsb>6</field_lsb>
    <rel_range>63:6</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-5_4" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>BANK</field_name>
    <field_msb>5</field_msb>
    <field_lsb>4</field_lsb>
    <rel_range>5:4</rel_range>
    <field_description order="before">
      <para>Breakpoint and watchpoint bank select.</para>
    </field_description>
    <field_description order="after"><para>Each of the following register names accesses a register for breakpoint or watchpoint &lt;n&gt;, where <value>n = UInt(MDSELR_EL1.BANK:m[3:0])</value>:</para>
<list type="unordered">
<listitem><content><register_link id="AArch64-dbgbcrn_el1.xml" state="AArch64">DBGBCR&lt;m&gt;_EL1</register_link>.</content>
</listitem><listitem><content><register_link id="AArch64-dbgbvrn_el1.xml" state="AArch64">DBGBVR&lt;m&gt;_EL1</register_link>.</content>
</listitem><listitem><content><register_link id="AArch64-dbgwcrn_el1.xml" state="AArch64">DBGWCR&lt;m&gt;_EL1</register_link>.</content>
</listitem><listitem><content><register_link id="AArch64-dbgwvrn_el1.xml" state="AArch64">DBGWVR&lt;m&gt;_EL1</register_link>.</content>
</listitem></list>
<para>This field is ignored by the PE and treated as zeros when any of the following are true:</para>
<list type="unordered">
<listitem><content>Executing at EL3 and <register_link state="AArch64" id="AArch64-mdcr_el3.xml">MDCR_EL3</register_link>.EBWE is 0.</content>
</listitem><listitem><content>Executing at EL2 and the Effective value of <register_link state="AArch64" id="AArch64-mdcr_el2.xml">MDCR_EL2</register_link>.EBWE is 0.</content>
</listitem><listitem><content>Executing at EL1 and the Effective value of <register_link state="AArch64" id="AArch64-mdscr_el1.xml">MDSCR_EL1</register_link>.EMBWE is 0.</content>
</listitem></list></field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b00</field_value>
        <field_value_description>
          <para>Select 0 to 15.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b01</field_value>
        <field_value_description>
          <para>Select 16 to 31.</para>
        </field_value_description>
        <field_value_condition>When NUM_BREAKPOINTS &gt; 16 or NUM_WATCHPOINTS &gt; 16</field_value_condition>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b10</field_value>
        <field_value_description>
          <para>Select 32 to 47.</para>
        </field_value_description>
        <field_value_condition>When NUM_BREAKPOINTS &gt; 32 or NUM_WATCHPOINTS &gt; 32</field_value_condition>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b11</field_value>
        <field_value_description>
          <para>Select 48 to 63.</para>
        </field_value_description>
        <field_value_condition>When NUM_BREAKPOINTS &gt; 48 or NUM_WATCHPOINTS &gt; 48</field_value_condition>
      </field_value_instance>
    </field_values>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
    <field_access>
      <field_access_state>
        <field_access_level operand="AND">
          <field_access_sublevel>NUM_BREAKPOINTS &lt;= 16</field_access_sublevel>
          <field_access_sublevel>NUM_WATCHPOINTS &lt;= 16</field_access_sublevel>
        </field_access_level>
        <field_access_type>
          <arm-defined-word>RES0</arm-defined-word>
        </field_access_type>
      </field_access_state>
      <field_access_state>
        <field_access_type>RW</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <field id="fieldset_0-3_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>3</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>3:0</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_6" msb="63" lsb="6"/>
  <fieldat id="fieldset_0-5_4" msb="5" lsb="4"/>
  <fieldat id="fieldset_0-3_0" msb="3" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>When 16 or fewer breakpoints are implemented, 16 or fewer watchpoints are implemented, and MDSELR_EL1 is implemented as RAZ/WI, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether these trap controls have any effect on accesses to MDSELR_EL1.</para>
      </access_permission_text>





    
        
        <access_mechanism accessor="MRS MDSELR_EL1" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, MDSELR_EL1</access_instruction>
                
                <enc n="op0" v="0b10"/>
                
                <enc n="op1" v="0b000"/>
                
                <enc n="CRn" v="0b0000"/>
                
                <enc n="CRm" v="0b0100"/>
                
                <enc n="op2" v="0b010"/>
            </encoding>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !(IsFeatureImplemented(FEAT_Debugv8p9) &amp;&amp; IsFeatureImplemented(FEAT_AA64)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().EBWE == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().TDA == '1' then
        Undefined();
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT2) &amp;&amp; ((HaveEL(EL3) &amp;&amp; SCR_EL3().FGTEn2 == '0') || HDFGRTR2_EL2().nMDSELR_EL1 == '0') then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; MDCR_EL2().[TDE,TDA] != '00' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().EBWE == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().TDA == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = MDSELR_EL1();
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().EBWE == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().TDA == '1' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().EBWE == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().TDA == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = MDSELR_EL1();
    end;
elsif PSTATE.EL == EL3 then
    X{64}(t) = MDSELR_EL1();
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MSRregister MDSELR_EL1" type="SystemAccessor">
            <encoding>
            <access_instruction>MSR MDSELR_EL1, &lt;Xt&gt;</access_instruction>
                
                <enc n="op0" v="0b10"/>
                
                <enc n="op1" v="0b000"/>
                
                <enc n="CRn" v="0b0000"/>
                
                <enc n="CRm" v="0b0100"/>
                
                <enc n="op2" v="0b010"/>
            </encoding>
            <access_permission>
                <ps name="MSRregister" sections="1" secttype="access_permission">
                <pstext>
if !(IsFeatureImplemented(FEAT_Debugv8p9) &amp;&amp; IsFeatureImplemented(FEAT_AA64)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().EBWE == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().TDA == '1' then
        Undefined();
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT2) &amp;&amp; ((HaveEL(EL3) &amp;&amp; SCR_EL3().FGTEn2 == '0') || HDFGWTR2_EL2().nMDSELR_EL1 == '0') then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; MDCR_EL2().[TDE,TDA] != '00' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().EBWE == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().TDA == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        MDSELR_EL1() = X{64}(t);
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().EBWE == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().TDA == '1' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().EBWE == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().TDA == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        MDSELR_EL1() = X{64}(t);
    end;
elsif PSTATE.EL == EL3 then
    MDSELR_EL1() = X{64}(t);
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>