<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>MPAM0_EL1</reg_short_name>
        
        <reg_long_name>MPAM0 Register (EL1)</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_MPAM is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Holds information to generate MPAM labels for memory requests when executing at EL0.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>MPAM</reg_group>
      </reg_groups>
      <reg_configuration>
        
    
      <configuration_text>
        <para>If FEAT_MPAM is implemented, EL2 is implemented and enabled in the current Security state, and the MPAM virtualization option is present, then:</para>

      </configuration_text>
      <configuration_text>
        <list type="unordered">
<listitem><content>
<para>If <register_link state="AArch64" id="AArch64-mpamhcr_el2.xml">MPAMHCR_EL2</register_link>.GSTAPP_PLK == 1 and the Effective value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.TGE is 0, <register_link state="AArch64" id="AArch64-mpam1_el1.xml">MPAM1_EL1</register_link> is used instead of MPAM0_EL1 to generate MPAM information to label memory requests.</para>
</content>
</listitem><listitem><content>
<para>If the Effective value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.{E2H, TGE} is not {1, 1} and <register_link state="AArch64" id="AArch64-mpamhcr_el2.xml">MPAMHCR_EL2</register_link>.EL0_VPMEN == 1, then MPAM PARTIDs in MPAM0_EL1 are virtual and mapped into physical PARTIDs for the current Security state.</para>
</content>
</listitem></list>
      </configuration_text>

      </reg_configuration>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>MPAM0_EL1 is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_48" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>63</field_msb>
    <field_lsb>48</field_lsb>
    <rel_range>63:48</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-47_40" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>PMG_D</field_name>
    <field_msb>47</field_msb>
    <field_lsb>40</field_lsb>
    <rel_range>47:40</rel_range>
    <field_description order="before">
      <para>Performance monitoring group property for PARTID_D.</para>
    </field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <field id="fieldset_0-39_32" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>PMG_I</field_name>
    <field_msb>39</field_msb>
    <field_lsb>32</field_lsb>
    <rel_range>39:32</rel_range>
    <field_description order="before">
      <para>Performance monitoring group property for PARTID_I.</para>
    </field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <field id="fieldset_0-31_16" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>PARTID_D</field_name>
    <field_msb>31</field_msb>
    <field_lsb>16</field_lsb>
    <rel_range>31:16</rel_range>
    <field_description order="before">
      <para>Partition ID for data accesses, including load and store accesses, made from EL0.</para>
    </field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <field id="fieldset_0-15_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>PARTID_I</field_name>
    <field_msb>15</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>15:0</rel_range>
    <field_description order="before">
      <para>Partition ID for instruction accesses made from EL0.</para>
    </field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_48" msb="63" lsb="48"/>
  <fieldat id="fieldset_0-47_40" msb="47" lsb="40"/>
  <fieldat id="fieldset_0-39_32" msb="39" lsb="32"/>
  <fieldat id="fieldset_0-31_16" msb="31" lsb="16"/>
  <fieldat id="fieldset_0-15_0" msb="15" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>None of the fields in this register are permitted to be cached in a TLB.</para>
      </access_permission_text>





    
        
        <access_mechanism accessor="MRS MPAM0_EL1" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, MPAM0_EL1</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b000"/>
                
                <enc n="CRn" v="0b1010"/>
                
                <enc n="CRm" v="0b0101"/>
                
                <enc n="op2" v="0b001"/>
            </encoding>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_MPAM) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) &amp;&amp; MPAM3_EL3().TRAPLOWER == '1' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) &amp;&amp; MPAM3_EL3().TRAPLOWER == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    elsif EL2Enabled() &amp;&amp; (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) &amp;&amp; MPAM2_EL2().TRAPMPAM0EL1 == '1' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    else
        X{64}(t) = MPAM0_EL1();
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) &amp;&amp; MPAM3_EL3().TRAPLOWER == '1' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) &amp;&amp; MPAM3_EL3().TRAPLOWER == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = MPAM0_EL1();
    end;
elsif PSTATE.EL == EL3 then
    X{64}(t) = MPAM0_EL1();
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MSRregister MPAM0_EL1" type="SystemAccessor">
            <encoding>
            <access_instruction>MSR MPAM0_EL1, &lt;Xt&gt;</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b000"/>
                
                <enc n="CRn" v="0b1010"/>
                
                <enc n="CRm" v="0b0101"/>
                
                <enc n="op2" v="0b001"/>
            </encoding>
            <access_permission>
                <ps name="MSRregister" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_MPAM) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) &amp;&amp; MPAM3_EL3().TRAPLOWER == '1' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) &amp;&amp; MPAM3_EL3().TRAPLOWER == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    elsif EL2Enabled() &amp;&amp; (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) &amp;&amp; MPAM2_EL2().TRAPMPAM0EL1 == '1' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    else
        MPAM0_EL1() = X{64}(t);
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) &amp;&amp; MPAM3_EL3().TRAPLOWER == '1' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) &amp;&amp; MPAM3_EL3().TRAPLOWER == '1' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        MPAM0_EL1() = X{64}(t);
    end;
elsif PSTATE.EL == EL3 then
    MPAM0_EL1() = X{64}(t);
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>