MPAM2_EL2 MPAM2 Register (EL2) when FEAT_MPAM is implemented MPAM3_EL3 Architectural AArch64 63 63 63 63 63 63 63 63 when (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented) and EL3 is implemented MPAM1_EL1 Architectural AArch64 63 63 63 63 63 63 63 63 when FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented Holds information to generate MPAM labels for memory requests when executing at EL2. MPAM This register has no effect on execution at EL1 and EL0, if EL2 is not enabled in the current Security state. MPAM2_EL2 is a 64-bit register. MPAMEN 63 63 63 MPAM Enable. MPAM is enabled when MPAMEN == 1. When disabled, all PARTIDs and PMGs are output as their default value in the corresponding ID space. If EL3 is implemented, this field is read-only and reads the current value of the read/write MPAM3_EL3.MPAMEN bit. 0b0 The default PARTID and default PMG are output in MPAM information from all Exception levels. 0b1 MPAM information is output based on the MPAMn_ELx register for ELn according to the MPAM configuration. '0' EL3 is implemented MPAM3_EL3.MPAMEN == '0' RAZ/WI EL3 is implemented MPAM3_EL3.MPAMEN == '1' RAO/WI When EL3 is not implemented RW 62 59 62:59 Reserved, RES0. TIDR 58 58 0 TIDR traps accesses to MPAMIDR_EL1 from EL1 to EL2. MPAMHCR_EL2.TRAP_MPAMIDR_EL1 == 1 also traps MPAMIDR_EL1 accesses from EL1 to EL2. If either TIDR or TRAP_MPAMIDR_EL1 are 1, accesses are trapped. 0b0 This control does not cause any instructions to be trapped. 0b1 Trap accesses to MPAMIDR_EL1 from EL1 to EL2. AU When (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented) and MPAMIDR_EL1.HAS_TIDR == '1' 58 58 58 Reserved, RES0. Otherwise 57 57 57 Reserved, RES0. ALTSP_HFC 56 56 0 Hierarchical force of alternative PARTID space controls. When MPAM3_EL3.ALTSP_HEN is 0, ALTSP controls in MPAM2_EL2 have no effect. When MPAM3_EL3.ALTSP_HEN is 1, this bit selects whether the PARTIDs in MPAM1_EL1 and MPAM0_EL1 are in the primary (0) or alternative (1) PARTID space for the security state. This control has no effect when MPAM3_EL3.ALTSP_HEN is 0. For more information, see 'In a PE with FEAT_RME, selection of primary or alternative PARTID space'. 0b0 When MPAM3_EL3.ALTSP_HEN is 1, the PARTID space of MPAM1_EL1.PARTID_I, MPAM1_EL1.PARTID_D, MPAM0_EL1.PARTID_I, and MPAM0_EL1.PARTID_D are in the primary PARTID space for the Security state. 0b1 When MPAM3_EL3.ALTSP_HEN is 1, the PARTID space of MPAM1_EL1.PARTID_I, MPAM1_EL1.PARTID_D, MPAM0_EL1.PARTID_I, and MPAM0_EL1.PARTID_D are in the alternative PARTID space for the Security state. AU When FEAT_RME is implemented and MPAMIDR_EL1.HAS_ALTSP == '1' 56 56 56 Reserved, RES0. Otherwise ALTSP_EL2 55 55 0 Select alternative PARTID space for PARTIDs in MPAM2_EL2 when MPAM3_EL3.ALTSP_HEN is 1. For more information, see 'In a PE with FEAT_RME, selection of primary or alternative PARTID space'. 0b0 When MPAM3_EL3.ALTSP_HEN is 1, selects the primary PARTID space for MPAM2_EL2.PARTID_I and MPAM2_EL2.PARTID_D. 0b1 When MPAM3_EL3.ALTSP_HEN is 1, selects the alternative PARTID space for MPAM2_EL2.PARTID_I and MPAM2_EL2.PARTID_D. AU When FEAT_RME is implemented and MPAMIDR_EL1.HAS_ALTSP == '1' 55 55 55 Reserved, RES0. Otherwise ALTSP_FRCD 54 54 0 Alternative PARTID forced for PARTIDs in this register. This bit indicates that a higher Exception level has forced the PARTIDs in this register to use the alternative PARTID space defined for the current Security state. In EL2, it is also 1 when MPAM2_EL2.ALTSP_EL2 is 1. For more information, see 'In a PE with FEAT_RME, selection of primary or alternative PARTID space'. 0b0 The PARTIDs in this register are using the primary PARTID space. 0b1 The PARTIDs in this register are using the alternative PARTID space. AU When !UsePrimarySpaceEL2() RAO/WI RAZ/WI When FEAT_RME is implemented and MPAMIDR_EL1.HAS_ALTSP == '1' 54 54 54 Reserved, RES0. Otherwise 53 51 53:51 Reserved, RES0. EnMPAMSM 50 50 0 Traps execution at EL1 of instructions that directly access the MPAMSM_EL1 register to EL2. The exception is reported using ESR_ELx.EC syndrome value 0x18. This field has no effect on accesses to MPAMSM_EL1 from EL2 or EL3. 0b0 This control causes execution of these instructions at EL1 to be trapped. 0b1 This control does not cause execution of any instructions to be trapped. AU When FEAT_SME is implemented 50 50 50 Reserved, RES0. Otherwise TRAPMPAM0EL1 49 49 49 Trap accesses from EL1 to the MPAM0_EL1 register trap to EL2. 0b0 Accesses to MPAM0_EL1 from EL1 are not trapped. 0b1 Accesses to MPAM0_EL1 from EL1 are trapped to EL2. '1' AU TRAPMPAM1EL1 48 48 48 Trap accesses from EL1 to the MPAM1_EL1 register trap to EL2. 0b0 Accesses to MPAM1_EL1 from EL1 are not trapped. 0b1 Accesses to MPAM1_EL1 from EL1 are trapped to EL2. '1' AU PMG_D 47 40 47:40 Performance monitoring group for data accesses. AU PMG_I 39 32 39:32 Performance monitoring group for instruction accesses. AU PARTID_D 31 16 31:16 Partition ID for data accesses, including load and store accesses, made from EL2. AU PARTID_I 15 0 15:0 Partition ID for instruction accesses made from EL2. AU When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name MPAM2_EL2 or MPAM1_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name. None of the fields in this register are permitted to be cached in a TLB. MRS <Xt>, MPAM2_EL2 if !IsFeatureImplemented(FEAT_MPAM) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else AArch64_SystemAccessTrap(EL2, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = MPAM2_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = MPAM2_EL2(); end; MSR MPAM2_EL2, <Xt> if !IsFeatureImplemented(FEAT_MPAM) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else AArch64_SystemAccessTrap(EL2, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else MPAM2_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then MPAM2_EL2() = X{64}(t); end; MRS <Xt>, MPAM1_EL1 if !IsFeatureImplemented(FEAT_MPAM) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM2_EL2().TRAPMPAM1EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x900); else X{64}(t) = MPAM1_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = MPAM2_EL2(); else X{64}(t) = MPAM1_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = MPAM1_EL1(); end; MSR MPAM1_EL1, <Xt> if !IsFeatureImplemented(FEAT_MPAM) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM2_EL2().TRAPMPAM1EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x900) = X{64}(t); else MPAM1_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then MPAM2_EL2() = X{64}(t); else MPAM1_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then MPAM1_EL1() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel