MPAMBW0_EL1 MPAM PE-side Maximum Bandwidth Control Register (EL0) when FEAT_MPAM_PE_BW_CTRL is implemented Enables software to configure a maximum fraction of memory bandwidth that the PE is permitted to use when executing at EL0 with its current PARTID. MPAM MPAMBW0_EL1 is a 64-bit register. HW_SCALE_ENABLE 63 63 0 Enables hardware bandwidth scaling of the MPAMBW0_EL1.MAX value. 0b0 PE-side memory bandwidth control hardware scaling at EL0 is disabled. 0b1 PE-side memory bandwidth control hardware scaling at EL0 is enabled. AU When MPAMBWIDR_EL1.HAS_HW_SCALE == '1' 63 63 63 Reserved, RES0. Otherwise ENABLED 62 62 62 Enables the PE-side memory bandwidth control when at EL0. 0b0 The PE-side memory bandwidth control at EL0 is disabled. 0b1 The PE-side memory bandwidth control at EL0 is enabled. AU HARDLIM 61 61 61 PE-side Maximum Bandwidth Limit Behavior Selection. 0b0 Soft limit: when MPAMBW0_EL1.MAX bandwidth is exceeded, the PE is unregulated unless the downstream memory path is saturated. It is IMPLEMENTATION DEFINED how hardware determines when the downstream memory path is saturated. 0b1 Hard limit: when MPAMBW0_EL1.MAX bandwidth is exceeded, the PE does not use any more bandwidth until the memory bandwidth for the PE falls below MPAMBW0_EL1.MAX. AU When MPAMBWIDR_EL1.MAX_LIM == '00' RW When MPAMBWIDR_EL1.MAX_LIM == '01' RAZ/WI When MPAMBWIDR_EL1.MAX_LIM == '10' RAO/WI 60 32 60:32 Reserved, RES0. MAX 31 0 31:0 When MPAMBWIDR_EL1.HAS_HW_SCALE == '1' and MPAMBW0_EL1.HW_SCALE_ENABLE == '1' MAX 31 0 31:0 Maximum memory bandwidth allocated to the PE when executing at EL0 with its current PARTID. The value is represented as a multiplier of the available bandwidth for the PE. The value is represented in base-2 fixed-point format. Bits [31:16] represent the integer part of the value. Bits [15:(16 - MPAMBWIDR_EL1.BWA_WD)] represent the fractional part of the value. When MPAMBWIDR_EL1.BWA_WD indicates a width less than 16 bits, bits [(15 - MPAMBWIDR_EL1.BWA_WD):0] are RES0. AU When MPAMBWIDR_EL1.HAS_HW_SCALE == '1' and MPAMBW0_EL1.HW_SCALE_ENABLE == '1' When MPAMBWIDR_EL1.HAS_HW_SCALE == '0' or MPAMBW0_EL1.HW_SCALE_ENABLE == '0' 31 16 31:16 Reserved, RES0. MAX 15 0 15:0 Maximum memory bandwidth allocated to the PE when executing at EL0 with its current PARTID. The value is represented as a fraction of the available bandwidth for the PE. The value is represented in base-2 fixed-point format. Bits [15:(16 - MPAMBWIDR_EL1.BWA_WD)] represent the fractional part of the value. When MPAMBWIDR_EL1.BWA_WD indicates a width less than 16 bits, bits [(15 - MPAMBWIDR_EL1.BWA_WD):0] are RES0. AU When MPAMBWIDR_EL1.HAS_HW_SCALE == '0' or MPAMBW0_EL1.HW_SCALE_ENABLE == '0' MRS <Xt>, MPAMBW0_EL1 if !IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MPAMBW3_EL3().nTRAPLOWER == '0' then Undefined(); elsif HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EL2Enabled() && MPAMBW2_EL2().nTRAP_MPAMBW0_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = MPAMBW0_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MPAMBW3_EL3().nTRAPLOWER == '0' then Undefined(); elsif HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = MPAMBW0_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = MPAMBW0_EL1(); end; MSR MPAMBW0_EL1, <Xt> if !IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MPAMBW3_EL3().nTRAPLOWER == '0' then Undefined(); elsif HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EL2Enabled() && MPAMBW2_EL2().nTRAP_MPAMBW0_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else MPAMBW0_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MPAMBW3_EL3().nTRAPLOWER == '0' then Undefined(); elsif HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else MPAMBW0_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then MPAMBW0_EL1() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel