MPAMBWCAP_EL2 MPAM PE-side Maximum Bandwidth Limit Virtualization Register when FEAT_MPAM_PE_BW_CTRL is implemented and MPAMIDR_EL1.HAS_HCR == '1' Allows software executing at EL2 to provide MPAMBWCAP_EL2.CAP as an upper bound to MPAMBW1_EL1.MAX. If FEAT_SME is implemented, the upper bound also applies to MPAMBWSM_EL1.MAX when executing at EL1: the maximum bandwidth allowed for the PE is MIN(MPAMBWSM_EL1.MAX, MPAMBWCAP_EL2.CAP). If the Effective value of HCR_EL2.{E2H,TGE} is not {1,1}: The upper bound also applies to MPAMBW0_EL1.MAX: the maximum bandwidth allowed for the PE is MIN(MPAMBW0_EL1.MAX, MPAMBWCAP_EL2.CAP). If FEAT_SME is implemented, the upper bound also applies to MPAMBWSM_EL1.MAX when executing at EL0: the maximum bandwidth allowed for the PE is MIN(MPAMBWSM_EL1.MAX, MPAMBWCAP_EL2.CAP). If MPAMBWCAP_EL2.ENABLED is 1, a PARTID that has used more than min(CAP,MAX) is given no access to additional bandwidth. MPAM This register has no effect if EL2 is not enabled in the current Security state. MPAMBWCAP_EL2 is a 64-bit register. HW_SCALE_ENABLE 63 63 0 Enables hardware bandwidth scaling of the MPAMBWCAP_EL2.CAP value. 0b0 PE-side memory bandwidth control hardware scaling for EL2 capping is disabled. 0b1 PE-side memory bandwidth control hardware scaling for EL2 capping is enabled. AU When MPAMBWIDR_EL1.HAS_HW_SCALE == '1' 63 63 63 Reserved, RES0. Otherwise ENABLED 62 62 62 Enables the PE-side memory bandwidth control capping by EL2. 0b0 The PE-side memory bandwidth control capping by EL2 is disabled. 0b1 The PE-side memory bandwidth control capping by EL2 is enabled. '0' AU 61 32 61:32 Reserved, RES0. CAP 31 0 31:0 When MPAMBWIDR_EL1.HAS_HW_SCALE == '1' and MPAMBWCAP_EL2.HW_SCALE_ENABLE == '1' CAP 31 0 31:0 Upper bound to the maximum memory bandwidth allocated to the current PARTID in MPAMBW1_EL1.MAX, MPAMBW0_EL1.MAX and MPAMBWSM_EL1.MAX. The value is represented as a multiplier of the available bandwidth for the PE. The value is represented in base-2 fixed-point format. Bits [31:16] represent the integer part of the value. Bits [15:(16 - MPAMBWIDR_EL1.BWA_WD)] represent the fractional part of the value. When MPAMBWIDR_EL1.BWA_WD indicates a width less than 16 bits, bits [(15 - MPAMBWIDR_EL1.BWA_WD):0] are RES0. The value set in the MAX field must be less than or equal to this upper bound. AU When MPAMBWIDR_EL1.HAS_HW_SCALE == '1' and MPAMBWCAP_EL2.HW_SCALE_ENABLE == '1' When MPAMBWIDR_EL1.HAS_HW_SCALE == '0' or MPAMBWCAP_EL2.HW_SCALE_ENABLE == '0' 31 16 31:16 Reserved, RES0. CAP 15 0 15:0 Upper bound to the maximum memory bandwidth allocated to the current PARTID in MPAMBW1_EL1.MAX, MPAMBW0_EL1.MAX and MPAMBWSM_EL1.MAX. The value is represented as a fraction of the available bandwidth for the PE. The value is represented in base-2 fixed-point format. Bits [15:(16 - MPAMBWIDR_EL1.BWA_WD)] represent the fractional part of the value. When MPAMBWIDR_EL1.BWA_WD indicates a width less than 16 bits, bits [(15 - MPAMBWIDR_EL1.BWA_WD):0] are RES0. The value set in the MAX field must be less than or equal to this upper bound. AU When MPAMBWIDR_EL1.HAS_HW_SCALE == '0' or MPAMBWCAP_EL2.HW_SCALE_ENABLE == '0' MRS <Xt>, MPAMBWCAP_EL2 if !(IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) && MPAMIDR_EL1().HAS_HCR == '1') then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x910); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else AArch64_SystemAccessTrap(EL2, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MPAMBW3_EL3().nTRAPLOWER == '0' then Undefined(); elsif HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = MPAMBWCAP_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = MPAMBWCAP_EL2(); end; MSR MPAMBWCAP_EL2, <Xt> if !(IsFeatureImplemented(FEAT_MPAM_PE_BW_CTRL) && MPAMIDR_EL1().HAS_HCR == '1') then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x910) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else AArch64_SystemAccessTrap(EL2, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MPAMBW3_EL3().nTRAPLOWER == '0' then Undefined(); elsif HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MPAMBW3_EL3().nTRAPLOWER == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else MPAMBWCAP_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then MPAMBWCAP_EL2() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel