MPAMIDR_EL1 MPAM ID Register (EL1) when FEAT_MPAM is implemented Indicates the maximum PARTID and PMG values supported in the implementation and the support for other optional features. Identification Registers MPAMIDR_EL1 is a 64-bit register. 63 62 63:62 Reserved, RES0. HAS_SDEFLT 61 61 61 HAS_SDEFLT indicates support for MPAM3_EL3.SDEFLT bit. When MPAM3_EL3.SDEFLT == 1, accesses from the Secure Execution state use the default PARTID, PARTID == 0. 0b0 The SDEFLT bit is not implemented in MPAM3_EL3. 0b1 The SDEFLT bit is implemented in MPAM3_EL3. RO HAS_FORCE_NS 60 60 60 HAS_FORCE_NS indicates support for MPAM3_EL3.FORCE_NS bit. When MPAM3_EL3.FORCE_NS == 1, accesses from the Secure Execution state have MPAM_NS == 1. 0b0 The FORCE_NS bit is not implemented in MPAM3_EL3. 0b1 The FORCE_NS bit is implemented in MPAM3_EL3. RO SP4 59 59 59 Supports 4 MPAM PARTID spaces. 0b0 MPAM supports 2 PARTID spaces. 0b1 MPAM supports 4 PARTID spaces. RO HAS_TIDR 58 58 58 HAS_TIDR indicates support for MPAM2_EL2.TIDR bit. Arm recommends that when the MPAM version is MPAM v0.1 or MPAM v1.1, MPAMIDR_EL1.HAS_TIDR is 1 and that the MPAM2_EL2.TIDR field is implemented. 0b0 The TIDR bit is not implemented in MPAM2_EL2. 0b1 The TIDR bit is implemented in MPAM2_EL2. RO HAS_ALTSP 57 57 57 HAS_ALTSP indicates support for alternative PARTID spaces. 0b0 Alternative PARTID spaces are not implemented. 0b1 Alternative PARTID spaces are implemented with control bits in MPAM3_EL3 and MPAM2_EL2. RO HAS_BW_CTRL 56 56 56 HAS_BW_CTRL indicates support for PE-side bandwidth controls. FEAT_MPAM_PE_BW_CTRL implements the functionality identified by the value 1. 0b0 PE-side bandwidth controls are not implemented. 0b1 PE-side bandwidth controls are implemented. RO 55 40 55:40 Reserved, RES0. PMG_MAX 39 32 39:32 The largest value of PMG that the implementation can generate. The PMG_I and PMG_D fields of every MPAMn_ELx must implement at least enough bits to represent PMG_MAX. This field has an IMPLEMENTATION DEFINED value. RO 31 21 31:21 Reserved, RES0. VPMR_MAX 20 18 2:0 Indicates the maximum register index n for the MPAMVPM<n>_EL2 registers. This field has an IMPLEMENTATION DEFINED value. RO When MPAMIDR_EL1.HAS_HCR == '1' 20 18 20:18 Reserved, RAZ. Otherwise HAS_HCR 17 17 17 HAS_HCR indicates that the PE implementation supports MPAM virtualization, including MPAMHCR_EL2, MPAMVPMV_EL2, and MPAMVPM<n>_EL2 with n in the range 0 to VPMR_MAX. Must be 0 if EL2 is not implemented in either Security state. 0b0 MPAM virtualization is not supported. 0b1 MPAM virtualization is supported. RO 16 16 16 Reserved, RES0. PARTID_MAX 15 0 15:0 The largest value of PARTID that the implementation can generate. The PARTID_I and PARTID_D fields of every MPAMn_ELx must implement at least enough bits to represent PARTID_MAX. This field has an IMPLEMENTATION DEFINED value. RO MRS <Xt>, MPAMIDR_EL1 if !IsFeatureImplemented(FEAT_MPAM) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAMIDR_EL1().HAS_HCR == '1' && MPAMHCR_EL2().TRAP_MPAMIDR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAMIDR_EL1().HAS_TIDR == '1' && MPAM2_EL2().TIDR == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = MPAMIDR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && (IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = MPAMIDR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = MPAMIDR_EL1(); end; 2026-03-26 20:27:25 2026-03_rel