MPIDR_EL1 Multiprocessor Affinity Register when FEAT_AA64 is implemented MPIDR Architectural AArch32 31 0 31 0 31 0 31 0 In a multiprocessor system, provides an additional PE identification mechanism. Identification Registers In a uniprocessor system, Arm recommends that each Aff<n> field of this register returns a value of 0. MPIDR_EL1 is a 64-bit register. 63 40 63:40 Reserved, RES0. Aff3 39 32 39:32 Affinity level 3. See the description of Aff0 for more information. Aff3 is not supported in AArch32 state. This field has an IMPLEMENTATION DEFINED value. RO 31 31 31 Reserved, RES1. U 30 30 30 Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system. 0b0 Processor is part of a multiprocessor system. 0b1 Processor is part of a uniprocessor system. RO 29 25 29:25 Reserved, RES0. MT 24 24 24 Indicates whether the lowest level of affinity consists of logical PEs that are implemented using an interdependent approach, such as multithreading. See the description of Aff0 for more information about affinity levels. This field does not indicate that multithreading is implemented and does not indicate that PEs with different affinity level 0 values, and the same values for affinity level 1 and higher are implemented. 0b0 Performance of PEs with different affinity level 0 values, and the same values for affinity level 1 and higher, is largely independent. 0b1 Performance of PEs with different affinity level 0 values, and the same values for affinity level 1 and higher, is very interdependent. RO Aff2 23 16 23:16 Affinity level 2. See the description of Aff0 for more information. This field has an IMPLEMENTATION DEFINED value. RO Aff1 15 8 15:8 Affinity level 1. See the description of Aff0 for more information. This field has an IMPLEMENTATION DEFINED value. RO Aff0 7 0 7:0 Affinity level 0. The value of the MPIDR.{Aff2, Aff1, Aff0} or MPIDR_EL1.{Aff3, Aff2, Aff1, Aff0} set of fields of each PE must be unique within the system as a whole. This field has an IMPLEMENTATION DEFINED value. RO MRS <Xt>, MPIDR_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().MPIDR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() then X{64}(t) = VMPIDR_EL2(); else X{64}(t) = MPIDR_EL1(); end; elsif PSTATE.EL == EL2 then X{64}(t) = MPIDR_EL1(); elsif PSTATE.EL == EL3 then X{64}(t) = MPIDR_EL1(); end; 2026-03-26 20:27:25 2026-03_rel