MVFR1_EL1
AArch32 Media and VFP Feature Register 1
when FEAT_AA64 is implemented
MVFR1
Architectural
AArch32
31
0
31
0
31
0
31
0
Describes the features provided by the AArch32 Advanced SIMD and floating-point implementation.
Must be interpreted with MVFR0_EL1 and MVFR2_EL1.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.
Float
In an implementation where at least one Exception level supports execution in AArch32 state, but there is no support for Advanced SIMD and floating-point operation, this register is RAZ.
MVFR1_EL1 is a 64-bit register.
When FEAT_AA32 is implemented
63
32
63:32
Reserved, RES0.
SIMDFMAC
31
28
31:28
Advanced SIMD Fused Multiply-Accumulate. Indicates whether the Advanced SIMD implementation provides fused multiply accumulate instructions.
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0001.
The Advanced SIMD and floating-point implementations must provide the same level of support for these instructions.
0b0000
Not implemented.
0b0001
Implemented.
RO
FPHP
27
24
27:24
Floating-Point Half-Precision. Indicates the level of half-precision floating-point support.
All other values are reserved.
In Armv8, the permitted values are:
0b0000 in an implementation without floating-point support.
0b0010 in an implementation with floating-point support that does not include the FEAT_FP16 extension.
0b0011 in an implementation with floating-point support that includes the FEAT_FP16 extension.
The level of support indicated by this field must be equivalent to the level of support indicated by the SIMDHP field, meaning the permitted values are:
Half-Precision instructions supportedFPHPSIMDHP
No support0b00000b0000
Conversions only0b00100b0001
Conversions and arithmetic0b00110b0010
0b0000
Not supported.
0b0001
Floating-point half-precision conversion instructions are supported for conversion between single-precision and half-precision.
0b0010
As for 0b0001, and adds instructions for conversion between double-precision and half-precision.
0b0011
As for 0b0010, and adds support for half-precision floating-point arithmetic.
RO
SIMDHP
23
20
23:20
Advanced SIMD Half-Precision. Indicates the level of half-precision floating-point support.
All other values are reserved.
In Armv8, the permitted values are:
0b0000 in an implementation without SIMD floating-point support.
0b0001 in an implementation with SIMD floating-point support that does not include the FEAT_FP16 extension.
0b0010 in an implementation with SIMD floating-point support that includes the FEAT_FP16 extension.
The level of support indicated by this field must be equivalent to the level of support indicated by the FPHP field, meaning the permitted values are:
Half-Precision instructions supportedFPHPSIMDHP
No support0b00000b0000
Conversions only0b00100b0001
Conversions and arithmetic0b00110b0010
0b0000
Not supported.
0b0001
SIMD half-precision conversion instructions are supported for conversion between single-precision and half-precision.
0b0010
As for 0b0001, and adds support for half-precision floating-point arithmetic.
RO
SIMDSP
19
16
19:16
Advanced SIMD Single-Precision. Indicates whether the Advanced SIMD and floating-point implementation provides single-precision floating-point instructions.
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0001.
0b0000
Not implemented.
0b0001
Implemented. This value is permitted only if the SIMDInt field is 0b0001.
RO
SIMDInt
15
12
15:12
Advanced SIMD Integer. Indicates whether the Advanced SIMD and floating-point implementation provides integer instructions.
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0001.
0b0000
Not implemented.
0b0001
Implemented.
RO
SIMDLS
11
8
11:8
Advanced SIMD Load/Store. Indicates whether the Advanced SIMD and floating-point implementation provides load/store instructions.
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0001.
0b0000
Not implemented.
0b0001
Implemented.
RO
FPDNaN
7
4
7:4
Default NaN mode. Indicates whether the floating-point implementation provides support only for the Default NaN mode.
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0001.
0b0000
Not implemented, or hardware supports only the Default NaN mode.
0b0001
Hardware supports propagation of NaN values.
RO
FPFtZ
3
0
3:0
Flush to Zero mode. Indicates whether the floating-point implementation provides support only for the Flush-to-Zero mode of operation.
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0001.
0b0000
Not implemented, or hardware supports only the Flush-to-Zero mode of operation.
0b0001
Hardware supports full denormalized number arithmetic.
RO
63
0
63:0
Reserved, UNKNOWN.
When FEAT_AA32 is implemented
MRS <Xt>, MVFR1_EL1
if !IsFeatureImplemented(FEAT_AA64) then
UnimplementedIDRegister();
elsif PSTATE.EL == EL0 then
if IsFeatureImplemented(FEAT_IDST) then
if EL2Enabled() && HCR_EL2().TGE == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
else
AArch64_SystemAccessTrap(EL1, 0x18);
end;
else
Undefined();
end;
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then
Undefined();
elsif EL2Enabled() && HCR_EL2().TID3 == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
X{64}(t) = MVFR1_EL1();
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then
Undefined();
elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_IDTE3) && SCR_EL3().TID3 == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
X{64}(t) = MVFR1_EL1();
end;
elsif PSTATE.EL == EL3 then
X{64}(t) = MVFR1_EL1();
end;
2026-03-26 20:27:25
2026-03_rel