OSDTRTX_EL1 OS Lock Data Transfer Register, Transmit when FEAT_AA64 is implemented DBGDTRTXext Architectural AArch32 31 0 31 0 31 0 31 0 Used for save/restore of DBGDTRTX_EL0. It is a component of the Debug Communications Channel. Debug OSDTRTX_EL1 is a 64-bit register. 63 32 63:32 Reserved, RES0. DTRTX 31 0 31:0 Return DTRTX without side-effect. Reads of this register return the value in DTRTX and do not change TXfull. Writes of this register update the value in DTRTX and do not change TXfull. For the full behavior of the Debug Communications Channel, see 'The Debug Communication Channel and Instruction Transfer Register'. Arm deprecates reads and writes of OSDTRTX_EL1 when the OS Lock is unlocked. MRS <Xt>, OSDTRTX_EL1 if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif Halted() && ConstrainUnpredictableBool(Unpredictable_IGNORETRAPINDEBUG) then X{64}(t) = OSDTRTX_EL1(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDA == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().[TDE,TDA] != '00' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = OSDTRTX_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDA == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = OSDTRTX_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = OSDTRTX_EL1(); end; MSR OSDTRTX_EL1, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif Halted() && ConstrainUnpredictableBool(Unpredictable_IGNORETRAPINDEBUG) then OSDTRTX_EL1() = X{64}(t); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDA == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().[TDE,TDA] != '00' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else OSDTRTX_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDA == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else OSDTRTX_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then OSDTRTX_EL1() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel