PAR_EL1
Physical Address Register
when FEAT_AA64 is implemented
PAR
Architectural
AArch32
63
0
63
0
63
0
63
0
Returns the output address (OA) from an Address translation instruction that executed successfully, or fault information if the instruction did not execute successfully.
Generic System Control
AArch64 System register PAR_EL1 is a 128-bit register that can also be accessed as a 64-bit value. If it is accessed as a 64-bit register, accesses read and write bits [63:0] and do not modify bits [127:64].
Single stage AT Instructions (ATS1*) report their result using the 128-bit format of PAR_EL1 if the translation system that they target uses VMSAv9-128.
ATS12* Instructions report their result using the 128-bit format PAR_EL1 if either of the following is true:
if stage 2 translations are enabled and the stage 2 translation system uses VMSAv9-128.
if stage 2 translations are disabled and the stage 1 translation system uses VMSAv9-128.
Otherwise, 64-bit format of PAR_EL1 is used.
PAR_EL1 is a:
128-bit register when FEAT_D128 is implemented, GetPAR_EL1_D128() == '1', and GetPAR_EL1_F() == '0'
128-bit register when FEAT_D128 is implemented, GetPAR_EL1_D128() == '1', and GetPAR_EL1_F() == '1'
128-bit register when FEAT_D128 is implemented, GetPAR_EL1_D128() == '0', and GetPAR_EL1_F() == '0'
128-bit register when FEAT_D128 is implemented, GetPAR_EL1_D128() == '0', and GetPAR_EL1_F() == '1'
64-bit register when FEAT_D128 is not implemented and GetPAR_EL1_F() == '0'
64-bit register when FEAT_D128 is not implemented and GetPAR_EL1_F() == '1'
When FEAT_D128 is implemented, GetPAR_EL1_D128() == '1', and GetPAR_EL1_F() == '0'
This section describes the register value returned by the successful execution of an Address translation instruction. Software might subsequently write a different value to the register, and that write does not affect the operation of the PE.
On a successful conversion, the PAR_EL1 can return a value that indicates the resulting attributes, rather than the values that appear in the Translation table descriptors. More precisely:
The PAR_EL1.{ATTR, SH} fields are permitted to report the resulting attributes, as determined by any permitted implementation choices and any applicable configuration bits, instead of reporting the values that appear in the Translation table descriptors.
See the PAR_EL1.NS bit description for constraints on the value it returns.
127
120
127:120
Reserved, RES0.
PA
119
76
119:76
Output address. The output address (OA) corresponding to the supplied input address. This field returns address bits[55:12].
AU
75
65
75:65
Reserved, RES0.
D128
64
64
64
Indicates if the PAR_EL1 uses the 128-bit format.
0b1
PAR_EL1 uses the 128-bit format. PAR_EL1[127:0] holds valid data.
AU
ATTR
63
56
63:56
Memory attributes for the returned output address. This field uses the same encoding as the Attr<n> fields in MAIR_EL1, MAIR_EL2, and MAIR_EL3.
If FEAT_MTE_PERM is implemented and the instruction performed a stage 2 translation, the following additional encoding is defined:
ATTRMeaning
0b11100000
Tagged NoTagAccess Normal Inner Write-Back, Outer Write-Back,
Read-Allocate, Write-Allocate Non-transient memory.
This encoding in MAIR_ELx is Reserved.The value returned in this field can be the resulting attribute that is actually implemented by the implementation, as determined by any permitted implementation choices and any applicable configuration bits, instead of the value that appears in the Translation table descriptor.
The attributes presented are consistent with the stages of translation applied in the address translation instruction. If the instruction performed a stage 1 translation only, the attributes are from the stage 1 translation. If the instruction performed a stage 1 and stage 2 translation, the attributes are from the combined stage 1 and stage 2 translation.
AU
55
52
55:52, 6:4
Reserved, RES0.
55
52
6
4
51
12
51:12
Reserved, RES0.
NSE
11
11
0
Reports the NSE attribute for a translation table descriptor from the EL3 translation regime.
For a description of the values derived by evaluating NS and NSE together, see PAR_EL1.NS.
For a result from a Secure, Non-secure, or Realm translation regime, this bit is unknown.
AU
When FEAT_RME is implemented
11
11
11
Reserved, RES1.
Otherwise
IMPLEMENTATION DEFINED
10
10
10
IMPLEMENTATION DEFINED.
AU
NS
9
9
0
Non-secure. The NS attribute for a translation table entry from a Secure translation regime, a Realm translation regime, and the EL3 translation regime.
For a result from an EL3 translation regime, NS and NSE are evaluated together to report the physical address space:
NSENSMeaning
0b00b0When Secure state is implemented, Secure. Otherwise reserved.
0b00b1Non-secure.
0b10b0Root.
0b10b1Realm.
For a result from a Secure translation regime, when SCR_EL3.EEL2 is 1, this bit distinguishes between the Secure and Non-secure intermediate physical address space of the translation for the instructions:
In AArch64 state: AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP, AT S1E0R, and AT S1E0W.
In AArch32 state: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP, ATS1CUR, and ATS1CUW.
Otherwise, this bit reflects the Security state of the physical address space of the translation. This means it reflects the effect of the NSTable bits of earlier levels of the translation table walk if those NSTable bits have an effect on the translation.
For a result from a Non-secure translation regime, this bit is UNKNOWN.
For a result from an S1E1 or S1E0 operation on the Realm EL1&0 translation regime, this bit is UNKNOWN.
AU
When FEAT_RME is implemented
NS
9
9
0
Non-secure. The NS attribute for a translation table entry from a Secure translation regime.
For a result from a Secure translation regime, when SCR_EL3.EEL2 is 1, this bit distinguishes between the Secure and Non-secure intermediate physical address space of the translation for the instructions:
In AArch64 state: AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP, AT S1E0R, and AT S1E0W.
In AArch32 state: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP, ATS1CUR, and ATS1CUW.
Otherwise, this bit reflects the Security state of the physical address space of the translation. This means it reflects the effect of the NSTable bits of earlier levels of the translation table walk if those NSTable bits have an effect on the translation.
For a result from a Non-secure translation regime, this bit is UNKNOWN.
AU
Otherwise
SH
8
7
8:7
Shareability attribute, for the returned output address.
The value 0b01 is reserved.
This field returns the value 0b10 for:Any type of Device memory.Normal memory with both Inner Non-cacheable and Outer Non-cacheable attributes.
The value returned in this field can be the resulting attribute, as determined by any permitted implementation choices and any applicable configuration bits, instead of the value that appears in the Translation table descriptor.
0b00
Non-shareable.
0b10
Outer Shareable.
0b11
Inner Shareable.
AU
6
4
55:52, 6:4
Reserved, RES0.
3
1
3:1
Reserved, RES0.
F
0
0
0
Indicates whether the instruction performed a successful address translation.
0b0
Address translation completed successfully.
AU
When FEAT_D128 is implemented, GetPAR_EL1_D128() == '1', and GetPAR_EL1_F() == '1'
This section describes the register value returned by a fault on the execution of an Address translation instruction. Software might subsequently write a different value to the register, and that write does not affect the operation of the PE.
127
65
127:65
Reserved, RES0.
D128
64
64
64
Indicates if the PAR_EL1 uses the 128-bit format.
0b1
PAR_EL1 uses the 128-bit format. PAR_EL1[127:0] holds valid data.
AU
IMPLEMENTATION DEFINED
63
56
63:56
IMPLEMENTATION DEFINED.
AU
IMPLEMENTATION DEFINED
55
52
55:52
IMPLEMENTATION DEFINED.
AU
IMPLEMENTATION DEFINED
51
48
51:48
IMPLEMENTATION DEFINED.
AU
47
16
47:16
Reserved, RES0.
DirtyBit
15
15
0
DirtyBit flag.
If PAR_EL1.FST indicates a Permission fault for a stage of translation that is using Indirect Permissions, and dirty state is managed by software, then this field holds information about the fault.
For any other fault or Access, this field is RES0.
At stage 1, dirty state is indicated by the nDirty bit in Block and Page descriptors. At stage 2, dirty state is indicated by the Dirty bit in Block and Page descriptors.
0b0
The Permission Fault is not due to dirty state.
0b1
The Permission Fault is due to dirty state.
AU
When FEAT_S1PIE is implemented or FEAT_S2PIE is implemented
15
15
15
Reserved, RES0.
Otherwise
Overlay
14
14
0
Overlay flag.
If PAR_EL1.FST indicates a Permission fault for a stage of translation, then this field holds information about the fault.
For any other fault, this field is RES0.
0b0
The Data Abort is not due to Overlay Permissions.
0b1
The Data Abort is due to Overlay Permissions.
AU
When FEAT_S1POE is implemented or FEAT_S2POE is implemented
14
14
14
Reserved, RES0.
Otherwise
TopLevel
13
13
0
Fault due to TopLevel. Indicates if the fault was due to TopLevel.
For any other fault, this field is RES0.
0b0
Fault is not due to TopLevel.
0b1
Fault is due to TopLevel.
AU
When FEAT_THE is implemented
13
13
13
Reserved, RES0.
Otherwise
AssuredOnly
12
12
0
AssuredOnly flag.
If PAR_EL1.S indicates a stage 2 fault, then this field holds information about the fault.
For any other fault, this field is RES0.
0b0
The Data Abort is not due to AssuredOnly.
0b1
The Data Abort is due to AssuredOnly.
AU
When FEAT_THE is implemented
12
12
12
Reserved, RES0.
Otherwise
11
11
11
Reserved, RES1.
10
10
10
Reserved, RES0.
S
9
9
9
Indicates the translation stage at which the translation aborted:
0b0
Translation aborted because of a fault in the stage 1 translation.
0b1
Translation aborted because of a fault in the stage 2 translation.
AU
PTW
8
8
8
If this bit is set to 1, it indicates the translation aborted because of a stage 2 fault during a stage 1 translation table walk.
AU
7
7
7
Reserved, RES0.
FST
6
1
6:1
Fault status code, as shown in the Data Abort ESR encoding.
The encodings for FST do not include Synchronous External abort on translation table walk or hardware update of translation table, because these MMU faults are reported as a Data Abort exception instead of being recorded in PAR_EL1. See Exceptions to reporting the fault in PAR_EL1.
0b000000
Address size fault, level 0 of translation or translation table base register.
0b000001
Address size fault, level 1.
0b000010
Address size fault, level 2.
0b000011
Address size fault, level 3.
0b000100
Translation fault, level 0.
0b000101
Translation fault, level 1.
0b000110
Translation fault, level 2.
0b000111
Translation fault, level 3.
0b001001
Access flag fault, level 1.
0b001010
Access flag fault, level 2.
0b001011
Access flag fault, level 3.
0b001000
Access flag fault, level 0.
When FEAT_LPA2 is implemented
0b001100
Permission fault, level 0.
When FEAT_LPA2 is implemented
0b001101
Permission fault, level 1.
0b001110
Permission fault, level 2.
0b001111
Permission fault, level 3.
0b011011
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level -1.
When FEAT_LPA2 is implemented and FEAT_RAS is not implemented
0b011100
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 0.
When FEAT_RAS is not implemented
0b011101
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 1.
When FEAT_RAS is not implemented
0b011110
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 2.
When FEAT_RAS is not implemented
0b011111
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 3.
When FEAT_RAS is not implemented
0b100010
Granule Protection Fault on translation table walk or hardware update of translation table, level -2.
When FEAT_D128 is implemented and FEAT_RME is implemented
0b100011
Granule Protection Fault on translation table walk or hardware update of translation table, level -1.
When FEAT_RME is implemented and FEAT_LPA2 is implemented
0b100100
Granule Protection Fault on translation table walk or hardware update of translation table, level 0.
When FEAT_RME is implemented
0b100101
Granule Protection Fault on translation table walk or hardware update of translation table, level 1.
When FEAT_RME is implemented
0b100110
Granule Protection Fault on translation table walk or hardware update of translation table, level 2.
When FEAT_RME is implemented
0b100111
Granule Protection Fault on translation table walk or hardware update of translation table, level 3.
When FEAT_RME is implemented
0b101000
Granule Protection Fault, not on translation table walk or hardware update of translation table.
When FEAT_RME is implemented
0b101001
Address size fault, level -1.
When FEAT_LPA2 is implemented
0b101010
Translation fault, level -2.
When FEAT_D128 is implemented
0b101011
Translation fault, level -1.
When FEAT_LPA2 is implemented
0b101100
Address Size fault, level -2.
When FEAT_D128 is implemented
0b110000
TLB conflict abort.
0b110001
Unsupported atomic hardware update fault.
When FEAT_HAF is implemented
0b111101
Section Domain fault, from an AArch32 stage 1 EL1&0 translation regime using Short-descriptor translation table format.
When FEAT_AA32EL1 is implemented
0b111110
Page Domain fault, from an AArch32 stage 1 EL1&0 translation regime using Short-descriptor translation table format.
When FEAT_AA32EL1 is implemented
AU
F
0
0
0
Indicates whether the instruction performed a successful address translation.
0b1
Address translation aborted.
AU
When FEAT_D128 is implemented, GetPAR_EL1_D128() == '0', and GetPAR_EL1_F() == '0'
This section describes the register value returned by the successful execution of an Address translation instruction. Software might subsequently write a different value to the register, and that write does not affect the operation of the PE.
On a successful conversion, the PAR_EL1 can return a value that indicates the resulting attributes, rather than the values that appear in the Translation table descriptors. More precisely:
The PAR_EL1.{ATTR, SH} fields are permitted to report the resulting attributes, as determined by any permitted implementation choices and any applicable configuration bits, instead of reporting the values that appear in the Translation table descriptors.
See the PAR_EL1.NS bit description for constraints on the value it returns.
127
65
127:65
Reserved, RES0.
D128
64
64
64
Indicates if the PAR_EL1 uses the 128-bit format.
0b0
PAR_EL1 uses the 64-bit format. PAR_EL1[63:0] holds valid data.
AU
ATTR
63
56
63:56
Memory attributes for the returned output address. This field uses the same encoding as the Attr<n> fields in MAIR_EL1, MAIR_EL2, and MAIR_EL3.
If FEAT_MTE_PERM is implemented and the instruction performed a stage 2 translation, the following additional encoding is defined:
ATTRMeaning
0b11100000
Tagged NoTagAccess Normal Inner Write-Back, Outer Write-Back,
Read-Allocate, Write-Allocate Non-transient memory.
This encoding in MAIR_ELx is Reserved.The value returned in this field can be the resulting attribute that is actually implemented by the implementation, as determined by any permitted implementation choices and any applicable configuration bits, instead of the value that appears in the Translation table descriptor.
The attributes presented are consistent with the stages of translation applied in the address translation instruction. If the instruction performed a stage 1 translation only, the attributes are from the stage 1 translation. If the instruction performed a stage 1 and stage 2 translation, the attributes are from the combined stage 1 and stage 2 translation.
AU
55
52
55:52, 6:4
Reserved, RES0.
55
52
6
4
PA[51:48]
51
48
3:0
Extension to PA[47:12]. For more information, see PA[47:12].
AU
When FEAT_LPA is implemented
51
48
51:48
Reserved, RES0.
Otherwise
PA[47:12]
47
12
47:12
Output address. The output address (OA) corresponding to the supplied input address. This field returns address bits[47:12].
When FEAT_LPA is implemented and 52-bit addresses are in use, PA[51:48] forms the upper part of the address value. Otherwise, when 52-bit addresses are not in use, PA[51:48] is RES0.
For implementations with fewer than 48 physical address bits, the corresponding upper bits in this field are RES0.
AU
NSE
11
11
0
Reports the NSE attribute for a translation table entry from the EL3 translation regime.
For a description of the values derived by evaluating NS and NSE together, see PAR_EL1.NS.
For a result from a Secure, Non-secure, or Realm translation regime, this bit is UNKNOWN.
AU
When FEAT_RME is implemented
11
11
11
Reserved, RES1.
Otherwise
IMPLEMENTATION DEFINED
10
10
10
IMPLEMENTATION DEFINED.
AU
NS
9
9
0
Non-secure. The NS attribute for a translation table entry from a Secure translation regime, a Realm translation regime, and the EL3 translation regime.
For a result from an EL3 translation regime, NS and NSE are evaluated together to report the physical address space:
NSENSMeaning
0b00b0When Secure state is implemented, Secure. Otherwise reserved.
0b00b1Non-secure.
0b10b0Root.
0b10b1Realm.
For a result from a Secure translation regime, when SCR_EL3.EEL2 is 1, this bit distinguishes between the Secure and Non-secure intermediate physical address space of the translation for the instructions:
In AArch64 state: AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP, AT S1E0R, and AT S1E0W.
In AArch32 state: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP, ATS1CUR, and ATS1CUW.
Otherwise, this bit reflects the Security state of the physical address space of the translation. This means it reflects the effect of the NSTable bits of earlier levels of the translation table walk if those NSTable bits have an effect on the translation.
For a result from a Non-secure translation regime, this bit is UNKNOWN.
For a result from an S1E1 or S1E0 operation on the Realm EL1&0 translation regime, this bit is UNKNOWN.
AU
When FEAT_RME is implemented
NS
9
9
0
Non-secure. The NS attribute for a translation table entry from a Secure translation regime.
For a result from a Secure translation regime, when SCR_EL3.EEL2 is 1, this bit distinguishes between the Secure and Non-secure intermediate physical address space of the translation for the instructions:
In AArch64 state: AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP, AT S1E0R, and AT S1E0W.
In AArch32 state: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP, ATS1CUR, and ATS1CUW.
Otherwise, this bit reflects the Security state of the physical address space of the translation. This means it reflects the effect of the NSTable bits of earlier levels of the translation table walk if those NSTable bits have an effect on the translation.
For a result from a Non-secure translation regime, this bit is UNKNOWN.
AU
Otherwise
SH
8
7
8:7
Shareability attribute, for the returned output address.
The value 0b01 is reserved.
This field returns the value 0b10 for:Any type of Device memory.Normal memory with both Inner Non-cacheable and Outer Non-cacheable attributes.
The value returned in this field can be the resulting attribute, as determined by any permitted implementation choices and any applicable configuration bits, instead of the value that appears in the Translation table descriptor.
0b00
Non-shareable.
0b10
Outer Shareable.
0b11
Inner Shareable.
AU
6
4
55:52, 6:4
Reserved, RES0.
3
1
3:1
Reserved, RES0.
F
0
0
0
Indicates whether the instruction performed a successful address translation.
0b0
Address translation completed successfully.
AU
When FEAT_D128 is implemented, GetPAR_EL1_D128() == '0', and GetPAR_EL1_F() == '1'
This section describes the register value returned by a fault on the execution of an Address translation instruction. Software might subsequently write a different value to the register, and that write does not affect the operation of the PE.
127
65
127:65
Reserved, RES0.
D128
64
64
64
Indicates if the PAR_EL1 uses the 128-bit format.
0b0
PAR_EL1 uses the 64-bit format. PAR_EL1[63:0] holds valid data.
AU
IMPLEMENTATION DEFINED
63
56
63:56
IMPLEMENTATION DEFINED.
AU
IMPLEMENTATION DEFINED
55
52
55:52
IMPLEMENTATION DEFINED.
AU
IMPLEMENTATION DEFINED
51
48
51:48
IMPLEMENTATION DEFINED.
AU
47
16
47:16
Reserved, RES0.
DirtyBit
15
15
0
DirtyBit flag.
If PAR_EL1.FST indicates a Permission fault for a stage of translation that is using Indirect Permissions, and dirty state is managed by software, then this field holds information about the fault.
For any other fault or Access, this field is RES0.
0b0
The Permission Fault is not due to nDirty State or Dirty State.
0b1
The Permission Fault is due to nDirty State or Dirty State.
AU
When FEAT_S1PIE is implemented or FEAT_S2PIE is implemented
15
15
15
Reserved, RES0.
Otherwise
Overlay
14
14
0
Overlay flag.
If PAR_EL1.FST indicates a Permission fault for a stage of translation, then this field holds information about the fault.
For any other fault, this field is RES0.
0b0
The Data Abort is not due to Overlay Permissions.
0b1
The Data Abort is due to Overlay Permissions.
AU
When FEAT_S1POE is implemented or FEAT_S2POE is implemented
14
14
14
Reserved, RES0.
Otherwise
TopLevel
13
13
0
Fault due to TopLevel. Indicates if the fault was due to TopLevel.
For any other fault, this field is RES0.
0b0
Fault is not due to TopLevel.
0b1
Fault is due to TopLevel.
AU
When FEAT_THE is implemented
13
13
13
Reserved, RES0.
Otherwise
AssuredOnly
12
12
0
AssuredOnly flag.
If PAR_EL1.S indicates a stage 2 fault, then this field holds information about the fault.
For any other fault, this field is RES0.
0b0
The Data Abort is not due to AssuredOnly.
0b1
The Data Abort is due to AssuredOnly.
AU
When FEAT_THE is implemented
12
12
12
Reserved, RES0.
Otherwise
11
11
11
Reserved, RES1.
10
10
10
Reserved, RES0.
S
9
9
9
Indicates the translation stage at which the translation aborted:
0b0
Translation aborted because of a fault in the stage 1 translation.
0b1
Translation aborted because of a fault in the stage 2 translation.
AU
PTW
8
8
8
If this bit is set to 1, it indicates the translation aborted because of a stage 2 fault during a stage 1 translation table walk.
AU
7
7
7
Reserved, RES0.
FST
6
1
6:1
Fault status code, as shown in the Data Abort exception ESR encoding.
The encodings for FST do not include Synchronous External abort on translation table walk or hardware update of translation table, because these MMU faults are reported as a Data Abort exception instead of being recorded in PAR_EL1. See Exceptions to reporting the fault in PAR_EL1.
0b000000
Address size fault, level 0 of translation or translation table base register.
0b000001
Address size fault, level 1.
0b000010
Address size fault, level 2.
0b000011
Address size fault, level 3.
0b000100
Translation fault, level 0.
0b000101
Translation fault, level 1.
0b000110
Translation fault, level 2.
0b000111
Translation fault, level 3.
0b001001
Access flag fault, level 1.
0b001010
Access flag fault, level 2.
0b001011
Access flag fault, level 3.
0b001000
Access flag fault, level 0.
When FEAT_LPA2 is implemented
0b001100
Permission fault, level 0.
When FEAT_LPA2 is implemented
0b001101
Permission fault, level 1.
0b001110
Permission fault, level 2.
0b001111
Permission fault, level 3.
0b011011
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level -1.
When FEAT_LPA2 is implemented and FEAT_RAS is not implemented
0b011100
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 0.
When FEAT_RAS is not implemented
0b011101
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 1.
When FEAT_RAS is not implemented
0b011110
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 2.
When FEAT_RAS is not implemented
0b011111
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 3.
When FEAT_RAS is not implemented
0b100010
Granule Protection Fault on translation table walk or hardware update of translation table, level -2.
When FEAT_D128 is implemented and FEAT_RME is implemented
0b100011
Granule Protection Fault on translation table walk or hardware update of translation table, level -1.
When FEAT_RME is implemented and FEAT_LPA2 is implemented
0b100100
Granule Protection Fault on translation table walk or hardware update of translation table, level 0.
When FEAT_RME is implemented
0b100101
Granule Protection Fault on translation table walk or hardware update of translation table, level 1.
When FEAT_RME is implemented
0b100110
Granule Protection Fault on translation table walk or hardware update of translation table, level 2.
When FEAT_RME is implemented
0b100111
Granule Protection Fault on translation table walk or hardware update of translation table, level 3.
When FEAT_RME is implemented
0b101000
Granule Protection Fault, not on translation table walk or hardware update of translation table.
When FEAT_RME is implemented
0b101001
Address size fault, level -1.
When FEAT_LPA2 is implemented
0b101010
Translation fault, level -2.
When FEAT_D128 is implemented
0b101011
Translation fault, level -1.
When FEAT_LPA2 is implemented
0b101100
Address Size fault, level -2.
When FEAT_D128 is implemented
0b110000
TLB conflict abort.
0b110001
Unsupported atomic hardware update fault.
When FEAT_HAF is implemented
0b111101
Section Domain fault, from an AArch32 stage 1 EL1&0 translation regime using Short-descriptor translation table format.
When FEAT_AA32EL1 is implemented
0b111110
Page Domain fault, from an AArch32 stage 1 EL1&0 translation regime using Short-descriptor translation table format.
When FEAT_AA32EL1 is implemented
AU
F
0
0
0
Indicates whether the instruction performed a successful address translation.
0b1
Address translation aborted.
AU
When FEAT_D128 is not implemented and GetPAR_EL1_F() == '0'
AArch64-PAR_EL1.F == 0b0
This section describes the register value returned by the successful execution of an Address translation instruction. Software might subsequently write a different value to the register, and that write does not affect the operation of the PE.
On a successful conversion, the PAR_EL1 can return a value that indicates the resulting attributes, rather than the values that appear in the Translation table descriptors. More precisely:
The PAR_EL1.{ATTR, SH} fields are permitted to report the resulting attributes, as determined by any permitted implementation choices and any applicable configuration bits, instead of reporting the values that appear in the Translation table descriptors.
See the PAR_EL1.NS bit description for constraints on the value it returns.
ATTR
63
56
63:56
Memory attributes for the returned output address. This field uses the same encoding as the Attr<n> fields in MAIR_EL1, MAIR_EL2, and MAIR_EL3.
If FEAT_MTE_PERM is implemented and the instruction performed a stage 2 translation, the following additional encoding is defined:
ATTRMeaning
0b11100000
Tagged NoTagAccess Normal Inner Write-Back, Outer Write-Back,
Read-Allocate, Write-Allocate Non-transient memory.
This encoding in MAIR_ELx is Reserved.The value returned in this field can be the resulting attribute that is actually implemented by the implementation, as determined by any permitted implementation choices and any applicable configuration bits, instead of the value that appears in the Translation table descriptor.
The attributes presented are consistent with the stages of translation applied in the address translation instruction. If the instruction performed a stage 1 translation only, the attributes are from the stage 1 translation. If the instruction performed a stage 1 and stage 2 translation, the attributes are from the combined stage 1 and stage 2 translation.
AU
55
52
55:52, 6:4
Reserved, RES0.
55
52
6
4
PA[51:48]
51
48
3:0
Extension to PA[47:12]. For more information, see PA[47:12].
AU
When FEAT_LPA is implemented
51
48
51:48
Reserved, RES0.
Otherwise
PA[47:12]
47
12
47:12
Output address. The output address (OA) corresponding to the supplied input address. This field returns address bits[47:12].
When FEAT_LPA is implemented and 52-bit addresses are in use, PA[51:48] forms the upper part of the address value. Otherwise, when 52-bit addresses are not in use, PA[51:48] is RES0.
For implementations with fewer than 48 physical address bits, the corresponding upper bits in this field are RES0.
AU
NSE
11
11
0
Reports the NSE attribute for a translation table entry from the EL3 translation regime.
For a description of the values derived by evaluating NS and NSE together, see PAR_EL1.NS.
For a result from a Secure, Non-secure, or Realm translation regime, this bit is UNKNOWN.
AU
When FEAT_RME is implemented
11
11
11
Reserved, RES1.
Otherwise
IMPLEMENTATION DEFINED
10
10
10
IMPLEMENTATION DEFINED.
AU
NS
9
9
0
Non-secure. The NS attribute for a translation table entry from a Secure translation regime, a Realm translation regime, and the EL3 translation regime.
For a result from an EL3 translation regime, NS and NSE are evaluated together to report the physical address space:
NSENSMeaning
0b00b0When Secure state is implemented, Secure. Otherwise reserved.
0b00b1Non-secure.
0b10b0Root.
0b10b1Realm.
For a result from a Secure translation regime, when SCR_EL3.EEL2 is 1, this bit distinguishes between the Secure and Non-secure intermediate physical address space of the translation for the instructions:
In AArch64 state: AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP, AT S1E0R, and AT S1E0W.
In AArch32 state: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP, ATS1CUR, and ATS1CUW.
Otherwise, this bit reflects the Security state of the physical address space of the translation. This means it reflects the effect of the NSTable bits of earlier levels of the translation table walk if those NSTable bits have an effect on the translation.
For a result from a Non-secure translation regime, this bit is UNKNOWN.
For a result from an S1E1 or S1E0 operation on the Realm EL1&0 translation regime, this bit is UNKNOWN.
AU
When FEAT_RME is implemented
NS
9
9
0
Non-secure. The NS attribute for a translation table entry from a Secure translation regime.
For a result from a Secure translation regime, when SCR_EL3.EEL2 is 1, this bit distinguishes between the Secure and Non-secure intermediate physical address space of the translation for the instructions:
In AArch64 state: AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP, AT S1E0R, and AT S1E0W.
In AArch32 state: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP, ATS1CUR, and ATS1CUW.
Otherwise, this bit reflects the Security state of the physical address space of the translation. This means it reflects the effect of the NSTable bits of earlier levels of the translation table walk if those NSTable bits have an effect on the translation.
For a result from a Non-secure translation regime, this bit is UNKNOWN.
AU
Otherwise
SH
8
7
8:7
Shareability attribute, for the returned output address.
The value 0b01 is reserved.
This field returns the value 0b10 for:Any type of Device memory.Normal memory with both Inner Non-cacheable and Outer Non-cacheable attributes.
The value returned in this field can be the resulting attribute, as determined by any permitted implementation choices and any applicable configuration bits, instead of the value that appears in the Translation table descriptor.
0b00
Non-shareable.
0b10
Outer Shareable.
0b11
Inner Shareable.
AU
6
4
55:52, 6:4
Reserved, RES0.
3
1
3:1
Reserved, RES0.
F
0
0
0
Indicates whether the instruction performed a successful address translation.
0b0
Address translation completed successfully.
AU
When FEAT_D128 is not implemented and GetPAR_EL1_F() == '1'
AArch64-PAR_EL1.F == 0b1
This section describes the register value returned by a fault on the execution of an Address translation instruction. Software might subsequently write a different value to the register, and that write does not affect the operation of the PE.
IMPLEMENTATION DEFINED
63
56
63:56
IMPLEMENTATION DEFINED.
AU
IMPLEMENTATION DEFINED
55
52
55:52
IMPLEMENTATION DEFINED.
AU
IMPLEMENTATION DEFINED
51
48
51:48
IMPLEMENTATION DEFINED.
AU
47
16
47:16
Reserved, RES0.
DirtyBit
15
15
0
DirtyBit flag.
If PAR_EL1.FST indicates a Permission fault for a stage of translation that is using Indirect Permissions, and dirty state is managed by software, then this field holds information about the fault.
For any other fault or Access, this field is RES0.
0b0
The Permission Fault is not due to nDirty State or Dirty State.
0b1
The Permission Fault is due to nDirty State or Dirty State.
AU
When FEAT_S1PIE is implemented or FEAT_S2PIE is implemented
15
15
15
Reserved, RES0.
Otherwise
Overlay
14
14
0
Overlay flag.
If PAR_EL1.FST indicates a Permission fault for a stage of translation, then this field holds information about the fault.
For any other fault, this field is RES0.
0b0
The Data Abort is not due to Overlay Permissions.
0b1
The Data Abort is due to Overlay Permissions.
AU
When FEAT_S1POE is implemented or FEAT_S2POE is implemented
14
14
14
Reserved, RES0.
Otherwise
TopLevel
13
13
0
Fault due to TopLevel. Indicates if the fault was due to TopLevel.
For any other fault, this field is RES0.
0b0
Fault is not due to TopLevel.
0b1
Fault is due to TopLevel.
AU
When FEAT_THE is implemented
13
13
13
Reserved, RES0.
Otherwise
AssuredOnly
12
12
0
AssuredOnly flag.
If PAR_EL1.S indicates a stage 2 fault, then this field holds information about the fault.
For any other fault, this field is RES0.
0b0
The Data Abort is not due to AssuredOnly.
0b1
The Data Abort is due to AssuredOnly.
AU
When FEAT_THE is implemented
12
12
12
Reserved, RES0.
Otherwise
11
11
11
Reserved, RES1.
10
10
10
Reserved, RES0.
S
9
9
9
Indicates the translation stage at which the translation aborted:
0b0
Translation aborted because of a fault in the stage 1 translation.
0b1
Translation aborted because of a fault in the stage 2 translation.
AU
PTW
8
8
8
If this bit is set to 1, it indicates the translation aborted because of a stage 2 fault during a stage 1 translation table walk.
AU
7
7
7
Reserved, RES0.
FST
6
1
6:1
Fault status code, as shown in the Data Abort exception ESR encoding.
The encodings for FST do not include Synchronous External abort on translation table walk or hardware update of translation table, because these MMU faults are reported as a Data Abort exception instead of being recorded in PAR_EL1. See Exceptions to reporting the fault in PAR_EL1.
0b000000
Address size fault, level 0 of translation or translation table base register.
0b000001
Address size fault, level 1.
0b000010
Address size fault, level 2.
0b000011
Address size fault, level 3.
0b000100
Translation fault, level 0.
0b000101
Translation fault, level 1.
0b000110
Translation fault, level 2.
0b000111
Translation fault, level 3.
0b001001
Access flag fault, level 1.
0b001010
Access flag fault, level 2.
0b001011
Access flag fault, level 3.
0b001000
Access flag fault, level 0.
When FEAT_LPA2 is implemented
0b001100
Permission fault, level 0.
When FEAT_LPA2 is implemented
0b001101
Permission fault, level 1.
0b001110
Permission fault, level 2.
0b001111
Permission fault, level 3.
0b011011
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level -1.
When FEAT_LPA2 is implemented and FEAT_RAS is not implemented
0b011100
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 0.
When FEAT_RAS is not implemented
0b011101
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 1.
When FEAT_RAS is not implemented
0b011110
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 2.
When FEAT_RAS is not implemented
0b011111
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 3.
When FEAT_RAS is not implemented
0b100010
Granule Protection Fault on translation table walk or hardware update of translation table, level -2.
When FEAT_D128 is implemented and FEAT_RME is implemented
0b100011
Granule Protection Fault on translation table walk or hardware update of translation table, level -1.
When FEAT_RME is implemented and FEAT_LPA2 is implemented
0b100100
Granule Protection Fault on translation table walk or hardware update of translation table, level 0.
When FEAT_RME is implemented
0b100101
Granule Protection Fault on translation table walk or hardware update of translation table, level 1.
When FEAT_RME is implemented
0b100110
Granule Protection Fault on translation table walk or hardware update of translation table, level 2.
When FEAT_RME is implemented
0b100111
Granule Protection Fault on translation table walk or hardware update of translation table, level 3.
When FEAT_RME is implemented
0b101000
Granule Protection Fault, not on translation table walk or hardware update of translation table.
When FEAT_RME is implemented
0b101001
Address size fault, level -1.
When FEAT_LPA2 is implemented
0b101010
Translation fault, level -2.
When FEAT_D128 is implemented
0b101011
Translation fault, level -1.
When FEAT_LPA2 is implemented
0b101100
Address Size fault, level -2.
When FEAT_D128 is implemented
0b110000
TLB conflict abort.
0b110001
Unsupported atomic hardware update fault.
When FEAT_HAF is implemented
0b111101
Section Domain fault, from an AArch32 stage 1 EL1&0 translation regime using Short-descriptor translation table format.
When FEAT_AA32EL1 is implemented
0b111110
Page Domain fault, from an AArch32 stage 1 EL1&0 translation regime using Short-descriptor translation table format.
When FEAT_AA32EL1 is implemented
AU
F
0
0
0
Indicates whether the instruction performed a successful address translation.
0b1
Address translation aborted.
AU
When FEAT_D128 is implemented, GetPAR_EL1_D128() == '1', and GetPAR_EL1_F() == '0'
When FEAT_D128 is implemented, GetPAR_EL1_D128() == '1', and GetPAR_EL1_F() == '1'
When FEAT_D128 is implemented, GetPAR_EL1_D128() == '0', and GetPAR_EL1_F() == '0'
When FEAT_D128 is implemented, GetPAR_EL1_D128() == '0', and GetPAR_EL1_F() == '1'
When FEAT_D128 is not implemented and GetPAR_EL1_F() == '0'
When FEAT_D128 is not implemented and GetPAR_EL1_F() == '1'
MRS <Xt>, PAR_EL1
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().PAR_EL1 == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
else
X{64}(t) = PAR_EL1()[63:0];
end;
elsif PSTATE.EL == EL2 then
X{64}(t) = PAR_EL1()[63:0];
elsif PSTATE.EL == EL3 then
X{64}(t) = PAR_EL1()[63:0];
end;
MSR PAR_EL1, <Xt>
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().PAR_EL1 == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
else
PAR_EL1()[63:0] = X{64}(t);
end;
elsif PSTATE.EL == EL2 then
PAR_EL1()[63:0] = X{64}(t);
elsif PSTATE.EL == EL3 then
PAR_EL1()[63:0] = X{64}(t);
end;
MRRS <Xt>, <Xt+1>, PAR_EL1
When FEAT_D128 is implemented
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().D128En == '0' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().PAR_EL1 == '1' then
AArch64_SystemAccessTrap(EL2, 0x14);
elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().D128En == '0') then
AArch64_SystemAccessTrap(EL2, 0x14);
elsif HaveEL(EL3) && SCR_EL3().D128En == '0' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x14);
end;
else
X{128}(t, t2) = PAR_EL1()[127:0];
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().D128En == '0' then
Undefined();
elsif HaveEL(EL3) && SCR_EL3().D128En == '0' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x14);
end;
else
X{128}(t, t2) = PAR_EL1()[127:0];
end;
elsif PSTATE.EL == EL3 then
X{128}(t, t2) = PAR_EL1()[127:0];
end;
MSRR PAR_EL1, <Xt>, <Xt+1>
When FEAT_D128 is implemented
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().D128En == '0' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().PAR_EL1 == '1' then
AArch64_SystemAccessTrap(EL2, 0x14);
elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().D128En == '0') then
AArch64_SystemAccessTrap(EL2, 0x14);
elsif HaveEL(EL3) && SCR_EL3().D128En == '0' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x14);
end;
else
PAR_EL1()[127:0] = X{128}(t, t2);
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().D128En == '0' then
Undefined();
elsif HaveEL(EL3) && SCR_EL3().D128En == '0' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x14);
end;
else
PAR_EL1()[127:0] = X{128}(t, t2);
end;
elsif PSTATE.EL == EL3 then
PAR_EL1()[127:0] = X{128}(t, t2);
end;
2026-03-26 20:27:25
2026-03_rel