PFAR_EL1
Physical Fault Address Register (EL1)
when FEAT_PFAR is implemented and FEAT_AA64 is implemented
Records the faulting physical address for a synchronous External abort, or SError exception taken to EL1.
Unknown
PFAR_EL1 is a 64-bit register.
NS
63
63
0
Together with PFAR_EL1.NSE, reports the physical address space of the access that triggered the exception.
NSENSMeaning
0b00b0When Secure state is implemented, Secure. Otherwise reserved.
0b00b1Non-secure.
0b10b0Reserved.
0b10b1Realm.
AU
When FEAT_RME is implemented
NS
63
63
0
Non-secure. Reports the physical address space of the access that triggered the exception.
0b0
Secure physical address space.
0b1
Non-secure physical address space.
AU
When EL3 is implemented or FEAT_Secure is implemented
63
63
63
Reserved, RES0.
Otherwise
NSE
62
62
0
Together with PFAR_EL1.NS, reports the physical address space of the access that triggered the exception.
For a description of the values derived by evaluating NS and NSE together, see MFAR_EL3.NS.
AU
When FEAT_RME is implemented
62
62
62
Reserved, RES0.
Otherwise
61
56
61:56
Reserved, RES0.
PA[55:52]
55
52
3:0
When FEAT_D128 is implemented, extension to PFAR_EL1.PA[47:0].
AU
When FEAT_D128 is implemented
55
52
55:52
Reserved, RES0.
Otherwise
PA[51:48]
51
48
3:0
When FEAT_LPA is implemented, extension to PFAR_EL1.PA[47:0].
AU
When FEAT_LPA is implemented
51
48
51:48
Reserved, RES0.
Otherwise
PA
47
0
47:0
Physical Address. Bits [47:0] of the aborting physical address.
For implementations with fewer than 48 physical address bits, the corresponding upper bits in this field are RES0.
The recorded address can be any address within the same naturally-aligned fault granule as the faulting physical address, where the size of the fault granule is IMPLEMENTATION DEFINED and no larger than the larger than:
The size of the range of values permitted to be recorded in FAR_EL1.
AU
When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name PFAR_EL1 or PFAR_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name.
PFAR_EL1 is not valid and reads UNKNOWN if ESR_EL1.PFV is recorded as 0.
MRS <Xt>, PFAR_EL1
if !(IsFeatureImplemented(FEAT_PFAR) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().PFAREn == '0' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nPFAR_EL1 == '0') then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && SCR_EL3().PFAREn == '0' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif EffectiveHCR_EL2_NVx() IN {'111'} then
X{64}(t) = NVMem(0x2D0);
else
X{64}(t) = PFAR_EL1();
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().PFAREn == '0' then
Undefined();
elsif HaveEL(EL3) && SCR_EL3().PFAREn == '0' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif ELIsInHost(EL2) then
X{64}(t) = PFAR_EL2();
else
X{64}(t) = PFAR_EL1();
end;
elsif PSTATE.EL == EL3 then
X{64}(t) = PFAR_EL1();
end;
MSR PFAR_EL1, <Xt>
if !(IsFeatureImplemented(FEAT_PFAR) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().PFAREn == '0' then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGWTR2_EL2().nPFAR_EL1 == '0') then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && SCR_EL3().PFAREn == '0' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif EffectiveHCR_EL2_NVx() IN {'111'} then
NVMem(0x2D0) = X{64}(t);
else
PFAR_EL1() = X{64}(t);
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().PFAREn == '0' then
Undefined();
elsif HaveEL(EL3) && SCR_EL3().PFAREn == '0' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif ELIsInHost(EL2) then
PFAR_EL2() = X{64}(t);
else
PFAR_EL1() = X{64}(t);
end;
elsif PSTATE.EL == EL3 then
PFAR_EL1() = X{64}(t);
end;
MRS <Xt>, PFAR_EL12
When FEAT_VHE is implemented
if !(IsFeatureImplemented(FEAT_PFAR) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EffectiveHCR_EL2_NVx() == '101' then
X{64}(t) = NVMem(0x2D0);
elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then
AArch64_SystemAccessTrap(EL2, 0x18);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
if ELIsInHost(EL2) then
if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().PFAREn == '0' then
Undefined();
elsif HaveEL(EL3) && SCR_EL3().PFAREn == '0' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
X{64}(t) = PFAR_EL1();
end;
else
Undefined();
end;
elsif PSTATE.EL == EL3 then
if ELIsInHost(EL2) then
X{64}(t) = PFAR_EL1();
else
Undefined();
end;
end;
MSR PFAR_EL12, <Xt>
When FEAT_VHE is implemented
if !(IsFeatureImplemented(FEAT_PFAR) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EffectiveHCR_EL2_NVx() == '101' then
NVMem(0x2D0) = X{64}(t);
elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then
AArch64_SystemAccessTrap(EL2, 0x18);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
if ELIsInHost(EL2) then
if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().PFAREn == '0' then
Undefined();
elsif HaveEL(EL3) && SCR_EL3().PFAREn == '0' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
PFAR_EL1() = X{64}(t);
end;
else
Undefined();
end;
elsif PSTATE.EL == EL3 then
if ELIsInHost(EL2) then
PFAR_EL1() = X{64}(t);
else
Undefined();
end;
end;
2026-03-26 20:27:25
2026-03_rel