PMBMAR_EL1
Profiling Buffer Memory Attribute Register
when FEAT_SPE_nVM is implemented
Controls Statistical Profiling Unit accesses to memory.
Configures some of the memory attributes of writes performed by the Statistical Profiling Unit.
TRBE
PMBMAR_EL1 is a 64-bit register.
63
10
63:10
Reserved, RES0.
SH
9
8
9:8
Profiling Buffer stage 1 shareability domain. Defines the shareability domain for Normal memory used by the Profiling Buffer.
All other values are reserved.
If the Profiling Buffer pointers specify virtual addresses, the memory attributes are defined by the translation tables and this field is ignored.
This field is ignored when PMBMAR_EL1.Attr specifies any of the following memory types:
Any Device memory type.
Normal memory, Inner Non-cacheable, Outer Non-cacheable.
All Device and Normal Inner Non-cacheable Outer Non-cacheable memory regions are always treated as Outer Shareable.
0b00
Non-shareable.
0b10
Outer Shareable.
0b11
Inner Shareable.
AU
Attr
7
0
7:0
Profiling Buffer stage 1 memory type and attributes. Defines the memory type and, for Normal memory, the cacheability attributes, for memory addressed by the Profiling Buffer.
The encoding of this field is the same as that of a MAIR_ELx.Attr<n> field, as follows:
AttrMeaning
0b0000dd00Device memory.
See encoding of 'dd' for the type of Device memory.
0b0000dd01If FEAT_XS is implemented:
Device memory with the XS attribute set to 0.
See encoding of 'dd' for the type of Device memory.
Otherwise,UNPREDICTABLE.
0b0000dd1xUNPREDICTABLE.
0booooiiiiwhere oooo != 0000
and iiii != 0000Normal memory. See encoding of 'oooo' and 'iiii' for the
type of Normal memory.
0b01000000If FEAT_XS is implemented:
Normal Inner Non-cacheable, Outer Non-cacheable memory
with the XS attribute set to 0.
Otherwise,UNPREDICTABLE.
0b10100000If FEAT_XS is implemented:
Normal Inner Write-through Cacheable, Outer Write-through Cacheable,
Read-Allocate, No-Write Allocate, Non-transient memory
with the XS attribute set to 0.
Otherwise,UNPREDICTABLE.
0b11110000If FEAT_MTE2 is implemented:
Tagged Normal Inner Write-Back, Outer Write-Back,
Read-Allocate, Write-Allocate Non-transient memory.
Otherwise,UNPREDICTABLE.
0bxxxx0000where xxxx != 0000
and xxxx != 0100
and xxxx != 1010
and xxxx != 1111UNPREDICTABLE.
dd is encoded as follows:
'dd'Meaning
0b00Device-nGnRnE memory.
0b01Device-nGnRE memory.
0b10Device-nGRE memory.
0b11Device-GRE memory.
oooo is encoded as follows:
'oooo'Meaning
0b0000See encoding of Attr.
0b00RWwhere RW != 00Normal memory, Outer Write-Through Transient.
0b0100Normal memory, Outer Non-cacheable.
0b01RWwhere RW != 00Normal memory, Outer Write-Back Transient.
0b10RWNormal memory, Outer Write-Through Non-transient.
0b11RWNormal memory, Outer Write-Back Non-transient.
R encodes the Outer Read-Allocate policy and W encodes the Outer Write-Allocate policy.
iiii is encoded as follows:
'iiii'Meaning
0b0000See encoding of Attr.
0b00RWwhere RW != 00Normal memory, Inner Write-Through Transient.
0b0100Normal memory, Inner Non-cacheable.
0b01RWwhere RW != 00Normal memory, Inner Write-Back Transient.
0b10RWNormal memory, Inner Write-Through Non-transient.
0b11RWNormal memory, Inner Write-Back Non-transient.
R encodes the Inner Read-Allocate policy and W encodes the Inner Write-Allocate policy.
In oooo and iiii, R and W are encoded as follows:
'R' or 'W'Meaning
0b0No Allocate.
0b1Allocate.
When FEAT_XS is implemented, stage 1 Inner Write-Back Cacheable, Outer Write-Back Cacheable memory types have the XS attribute set to 0.
If the Profiling Buffer pointers specify virtual addresses, the memory attributes are defined by the translation tables and this field is ignored.
AU
MRS <Xt>, PMBMAR_EL1
if !IsFeatureImplemented(FEAT_SPE_nVM) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPMS4 == '0' then
Undefined();
elsif HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGRTR2_EL2().nPMBMAR_EL1 == '0') then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && MDCR_EL2().E2PB IN {'x0'} then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && MDCR_EL3().EnPMS4 == '0' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
X{64}(t) = PMBMAR_EL1();
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then
Undefined();
elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPMS4 == '0' then
Undefined();
elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif HaveEL(EL3) && MDCR_EL3().EnPMS4 == '0' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
X{64}(t) = PMBMAR_EL1();
end;
elsif PSTATE.EL == EL3 then
X{64}(t) = PMBMAR_EL1();
end;
MSR PMBMAR_EL1, <Xt>
if !IsFeatureImplemented(FEAT_SPE_nVM) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPMS4 == '0' then
Undefined();
elsif HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then
Undefined();
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGWTR2_EL2().nPMBMAR_EL1 == '0') then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && MDCR_EL2().E2PB IN {'x0'} then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && MDCR_EL3().EnPMS4 == '0' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
PMBMAR_EL1() = X{64}(t);
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then
Undefined();
elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPMS4 == '0' then
Undefined();
elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif HaveEL(EL3) && MDCR_EL3().EnPMS4 == '0' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
PMBMAR_EL1() = X{64}(t);
end;
elsif PSTATE.EL == EL3 then
PMBMAR_EL1() = X{64}(t);
end;
2026-03-26 20:27:25
2026-03_rel