PMCEID1_EL0 Performance Monitors Common Event Identification Register 1 when FEAT_PMUv3 is implemented and FEAT_AA64 is implemented PMCEID1 Architectural AArch32 31 0 31 0 31 0 31 0 PMCEID3 Architectural AArch32 63 32 31 0 63 32 31 0 PMCEID1 Architectural External 31 0 31 0 31 0 31 0 PMCEID3 Architectural External 63 32 31 0 63 32 31 0 Defines which Common architectural events and Common microarchitectural events are implemented, or counted, using PMU events in the ranges 0x0020 to 0x003F and 0x4020 to 0x403F. For more information about the Common events and the use of the PMCEID<n>_EL0 registers see 'The PMU event number space and common events'. PMU PMCEID1_EL0 is a 64-bit register. IDhi<n> 63 32 31:0 IDhi[n] corresponds to Common event (0x4020 + n). For each bit: When the value of a bit in the field is 1, the corresponding Common event is implemented and counted. Arm recommends that if a Common event is never counted, the value of the corresponding bit is 0.A bit that corresponds to a reserved event number is reserved. The value might be used in a future revision of the architecture to identify an additional Common event. Such an event might be added retrospectively to an earlier version of the PMU architecture, provided the event does not require any additional PMU features and has an event number that can be represented in the PMCEID<n>_EL0 registers of that earlier version of the PMU architecture. 31 0 0b0 The Common event is not implemented, or not counted. 0b1 The Common event is implemented. When FEAT_PMUv3p1 is implemented 63 32 63:32 Reserved, RES0. Otherwise ID<n> 31 0 31:0 ID[n] corresponds to Common event (0x0020 + n). For each bit: When the value of a bit in the field is 1, the corresponding Common event is implemented and counted. Arm recommends that if a Common event is never counted, the value of the corresponding bit is 0.A bit that corresponds to a reserved event number is reserved. The value might be used in a future revision of the architecture to identify an additional Common event. Such an event might be added retrospectively to an earlier version of the PMU architecture, provided the event does not require any additional PMU features and has an event number that can be represented in the PMCEID<n>_EL0 registers of that earlier version of the PMU architecture. 31 0 0b0 The Common event is not implemented, or not counted. 0b1 The Common event is implemented. MRS <Xt>, PMCEID1_EL0 if !(IsFeatureImplemented(FEAT_PMUv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif PMUSERENR_EL0().EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0().UEN == '0') then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0().TID == '1' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMCEIDn_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMCEID1_EL0(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMCEIDn_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMCEID1_EL0(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMCEID1_EL0(); end; elsif PSTATE.EL == EL3 then X{64}(t) = PMCEID1_EL0(); end; 2026-03-26 20:27:25 2026-03_rel