PMCNTENSET_EL0 Performance Monitors Count Enable Set Register when FEAT_PMUv3 is implemented and FEAT_AA64 is implemented PMCNTENCLR_EL0 Architectural AArch64 63 0 63 0 63 0 63 0 PMCNTENSET Architectural AArch32 31 0 31 0 31 0 31 0 PMCNTENCLR Architectural AArch32 31 0 31 0 31 0 31 0 PMCNTENSET_EL0 Architectural External 31 0 31 0 31 0 31 0 PMCNTENCLR_EL0 Architectural External 31 0 31 0 31 0 31 0 PMCNTENSET_EL0 Architectural External 63 32 63 32 63 32 63 32 when FEAT_PMUv3p9 is implemented or FEAT_PMUv3_EXT64 is implemented PMCNTENCLR_EL0 Architectural External 63 32 63 32 63 32 63 32 when FEAT_PMUv3p9 is implemented or FEAT_PMUv3_EXT64 is implemented Allows software to enable the following counters: The cycle counter PMCCNTR_EL0. The event counters PMEVCNTR<n>_EL0. When FEAT_PMUv3_ICNTR is implemented, the instruction counter PMICNTR_EL0. Reading from this register shows which counters are enabled. PMU PMCNTENSET_EL0 is a 64-bit register. 63 33 63:33 Reserved, RES0. F0 32 32 0 PMICNTR_EL0 enable. On writes, allows software to enable PMICNTR_EL0. On reads, returns the PMICNTR_EL0 enable status. 0b0 PMICNTR_EL0 disabled. 0b1 PMICNTR_EL0 enabled. '0' EL3 is implemented PSTATE.EL != EL3 MDCR_EL3.EnPM2 == '0' RAZ/WI EL0 is the current Exception level PMUSERENR_EL0.UEN == '0' or PMUACR_EL1.F0 == '0' RAZ/WI FEAT_FGT2 is implemented EL2Enabled() PSTATE.EL IN {EL1, EL0} HCR_EL2.[E2H,TGE] != '11' (EL3 is implemented and SCR_EL3.FGTEn2 == '0') or (HDFGRTR2_EL2.nPMICFILTR_EL0 == '0' and HDFGWTR2_EL2.nPMICFILTR_EL0 == '0') RAZ/WI FEAT_FGT2 is implemented EL2Enabled() EL0 is the current Exception level HCR_EL2.[E2H,TGE] != '11' (EL3 is implemented and SCR_EL3.FGTEn2 == '0') or HDFGRTR2_EL2.nPMICFILTR_EL0 == '0' PMUSERENR_EL0.IR == '1' RAZ/WI FEAT_FGT2 is implemented EL2Enabled() PSTATE.EL IN {EL1, EL0} HCR_EL2.[E2H,TGE] != '11' (EL3 is implemented and SCR_EL3.FGTEn2 == '0') or HDFGRTR2_EL2.nPMICFILTR_EL0 == '0' WO/RAZ FEAT_FGT2 is implemented EL2Enabled() PSTATE.EL IN {EL1, EL0} HCR_EL2.[E2H,TGE] != '11' (EL3 is implemented and SCR_EL3.FGTEn2 == '0') or HDFGWTR2_EL2.nPMICFILTR_EL0 == '0' RO EL0 is the current Exception level PMUSERENR_EL0.IR == '1' RO W1S When FEAT_PMUv3_ICNTR is implemented 32 32 32 Reserved, RES0. Otherwise C 31 31 31 PMCCNTR_EL0 enable. On writes, allows software to enable PMCCNTR_EL0. On reads, returns the PMCCNTR_EL0 enable status. 0b0 PMCCNTR_EL0 disabled. 0b1 PMCCNTR_EL0 enabled. AU AU FEAT_PMUv3p9 is implemented EL0 is the current Exception level PMUSERENR_EL0.UEN == '1' PMUACR_EL1.C == '0' RAZ/WI FEAT_PMUv3p9 is implemented EL0 is the current Exception level PMUSERENR_EL0.[UEN,CR] == '11' RO W1S P<m> 30 0 30:0 PMEVCNTR<m>_EL0 enable. On writes, allows software to enable PMEVCNTR<m>_EL0. On reads, returns the PMEVCNTR<m>_EL0 enable status. 30 0 0b0 PMEVCNTR<m>_EL0 disabled. 0b1 PMEVCNTR<m>_EL0 enabled. AU AU When m >= GetNumEventCountersAccessible() RAZ/WI FEAT_PMUv3p9 is implemented EL0 is the current Exception level PMUSERENR_EL0.UEN == '1' PMUACR_EL1.P<m> == '0' RAZ/WI FEAT_PMUv3p9 is implemented EL0 is the current Exception level PMUSERENR_EL0.[UEN,ER] == '11' RO W1S MRS <Xt>, PMCNTENSET_EL0 if !(IsFeatureImplemented(FEAT_PMUv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif PMUSERENR_EL0().EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0().UEN == '0') then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMCNTEN == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMCNTENSET_EL0(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMCNTEN == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMCNTENSET_EL0(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMCNTENSET_EL0(); end; elsif PSTATE.EL == EL3 then X{64}(t) = PMCNTENSET_EL0(); end; MSR PMCNTENSET_EL0, <Xt> if !(IsFeatureImplemented(FEAT_PMUv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif PMUSERENR_EL0().EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0().UEN == '0') then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMCNTEN == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMCNTENSET_EL0() = X{64}(t); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMCNTEN == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMCNTENSET_EL0() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMCNTENSET_EL0() = X{64}(t); end; elsif PSTATE.EL == EL3 then PMCNTENSET_EL0() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel