PMCR_EL0 Performance Monitors Control Register when FEAT_PMUv3 is implemented and FEAT_AA64 is implemented PMCR Architectural AArch32 31 0 31 0 31 0 31 0 PMCR_EL0 Architectural External 31 0 31 0 31 0 31 0 PMCR_EL0 Architectural External 63 32 63 32 63 32 63 32 when FEAT_PMUv3_EXT64 is implemented Provides details of the Performance Monitors implementation, including the number of counters implemented, and configures and controls the counters. PMU PMCR_EL0 is a 64-bit register. 63 33 63:33 Reserved, RES0. FZS 32 32 0 Freeze-on-SPE event. Stop counters when PMBLIMITR_EL1.{PMFZ,E} is {1,1} and profiling is stopped. The pseudocode function SPEProfilingStopped() describes when profiling is stopped. The counters affected by this field are: The event counters in the first range. If FEAT_PMUv3_ICNTR is implemented, the instruction counter PMICNTR_EL0. If FEAT_SPE_DPFZS is implemented and PMCR_EL0.DP is 1, the cycle counter PMCCNTR_EL0. Other event counters are not affected by this field. When FEAT_SPE_DPFZS is not implemented or PMCR_EL0.DP is 0, PMCCNTR_EL0 is not affected by this field. For more information about event counter ranges, see MDCR_EL2.HPMN. 0b0 Do not freeze on a Statistical Profiling Buffer Management event. 0b1 Affected counters do not count following a Statistical Profiling Buffer Management event. '0' AU When FEAT_SPEv1p2 is implemented 32 32 32 Reserved, RES0. Otherwise IMP 31 24 7:0 Implementer code. If this field is zero, then PMCR_EL0.IDCODE is RES0 and software must use MIDR_EL1 to identify the PE. Otherwise, this field and PMCR_EL0.IDCODE identify the PMU implementation to software. The implementer codes are allocated by Arm. A nonzero value has the same interpretation as MIDR_EL1.Implementer. Arm deprecates use of this field. This field has an IMPLEMENTATION DEFINED value. RO When FEAT_PMUv3p7 is not implemented 31 24 31:24 Reserved, RAZ. Otherwise IDCODE 23 16 7:0 Identification code. Arm deprecates use of this field. Each implementer must maintain a list of identification codes that are specific to the implementer. A specific implementation is identified by the combination of the implementer code and the identification code. This field has an IMPLEMENTATION DEFINED value. RO When PMCR_EL0.IMP != '00000000' 23 16 23:16 Reserved, RES0. Otherwise N 15 11 15:11 Indicates the number of event counters implemented. This value is in the range of 0b00000-0b11111. If the value is 0b00000, then only PMCCNTR_EL0 is implemented. If the value is 0b11111, then PMCCNTR_EL0 and 31 event counters are implemented. When EL2 is implemented and enabled for the current Security state, reads of this field from EL1 and EL0 return the Effective value of MDCR_EL2.HPMN. This field has an IMPLEMENTATION DEFINED value. RO 10 10 10 Reserved, RES0. FZO 9 9 0 Freeze-on-overflow. Stop event counters on overflow. The counters affected by this field are: The event counters in the first range. If FEAT_PMUv3_ICNTR is implemented, the instruction counter PMICNTR_EL0. If PMCR_EL0.DP is 1, the cycle counter PMCCNTR_EL0. Other event counters are not affected by this field. When PMCR_EL0.DP is 0, PMCCNTR_EL0 is not affected by this field. For more information about event counter ranges, see MDCR_EL2.HPMN. 0b0 Do not freeze on overflow. 0b1 Affected counters do not count when any of the following applies: For any event counter PMEVCNTR<m>_EL0 in the first range, PMOVSCLR_EL0[m] is 1. FEAT_PMUv3_ICNTR is implemented and PMOVSCLR_EL0.F0 is 1. AU When FEAT_PMUv3p7 is implemented 9 9 9 Reserved, RES0. Otherwise 8 8 8 Reserved, RES0. LP 7 7 0 Long event counter enable. Determines when unsigned overflow is recorded by PMOVSCLR_EL0.P[n]. When FEAT_EBEP is implemented and the PMU Profiling exception is enabled, the Effective value of this field is 1. The counters affected by this field are the event counters in the first range. For more information about event counter ranges, see MDCR_EL2.HPMN. Other event counters and PMCCNTR_EL0 are not affected by this field. When FEAT_PMUv3_ICNTR is implemented, PMICNTR_EL0 is not affected by this field. 0b0 Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>_EL0[31:0]. 0b1 Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>_EL0[63:0]. AU When FEAT_PMUv3p5 is implemented 7 7 7 Reserved, RES0. Otherwise LC 6 6 0 Long cycle counter enable. Determines when unsigned overflow is recorded by PMOVSCLR_EL0.C. When FEAT_EBEP is implemented and the PMU Profiling exception is enabled, the Effective value of this field is 1. Arm deprecates use of PMCR_EL0.LC = 0. 0b0 Cycle counter overflow on increment that causes unsigned overflow of PMCCNTR_EL0[31:0]. 0b1 Cycle counter overflow on increment that causes unsigned overflow of PMCCNTR_EL0[63:0]. AU When FEAT_AA32 is implemented 6 6 6 Reserved, RES1. Otherwise DP 5 5 0 Disable cycle counter when event counting is prohibited. The conditions when this field disables the cycle counter are the same as when event counting by an event counter in the first range is prohibited or frozen. For more information about event counter ranges, see MDCR_EL2.HPMN. If FEAT_PMUv3p7 and FEAT_SPEv1p2 are implemented, meaning PMCR_EL0.FZS is implemented, and FEAT_SPE_DPFZS is not implemented, then cycle counting by PMCCNTR_EL0 is not affected by PMCR_EL0.FZS. For more information, see 'Prohibiting event and cycle counting'. 0b0 Cycle counting by PMCCNTR_EL0 is not affected by this mechanism. 0b1 Cycle counting by PMCCNTR_EL0 is disabled in prohibited regions and when event counting is frozen: If FEAT_PMUv3p1 is implemented, EL2 is implemented, and MDCR_EL2.HPMD is 1, then cycle counting by PMCCNTR_EL0 is disabled at EL2. If FEAT_SPE_DPFZS is implemented and event counting is frozen by PMCR_EL0.FZS, then cycle counting by PMCCNTR_EL0 is disabled. If FEAT_PMUv3p7 is implemented and event counting is frozen by PMCR_EL0.FZO, then cycle counting by PMCCNTR_EL0 is disabled. If FEAT_PMUv3p7 is implemented, EL3 is implemented, and MDCR_EL3.MPMX is 1, then cycle counting by PMCCNTR_EL0 is disabled at EL3. If EL3 is implemented, MDCR_EL3.SPME is 0, and either FEAT_PMUv3p7 is not implemented or MDCR_EL3.MPMX is 0, then cycle counting by PMCCNTR_EL0 is disabled at EL3 and in Secure state. AU When EL3 is implemented, or (FEAT_PMUv3p1 is implemented and EL2 is implemented), or FEAT_PMUv3p7 is implemented, or FEAT_SPE_DPFZS is implemented 5 5 5 Reserved, RES0. Otherwise X 4 4 0 Enable export of events in an IMPLEMENTATION DEFINED PMU event export bus. This field enables the exporting of events over an IMPLEMENTATION DEFINED PMU event export bus to another device. No events are exported when counting is prohibited. This field does not affect the generation of Performance Monitors overflow interrupt requests or signaling to a cross-trigger interface (CTI) that can be implemented as signals exported from the PE. If FEAT_ETE is implemented, this field does not affect the use of PMU events as an External Input by the trace unit. If FEAT_ETMv4 is implemented, this field does affect the use of PMU events as an External Input by the trace unit. 0b0 Do not export events. 0b1 Export events where not prohibited. AU When the implementation includes a PMU event export bus 4 4 4 Reserved, RAZ/WI. Otherwise D 3 3 0 Clock divider. If the Effective value of PMCR_EL0.LC is 1, then this field is ignored and the cycle counter counts every clock cycle. Arm deprecates use of PMCR_EL0.D = 1. 0b0 When enabled, PMCCNTR_EL0 counts every clock cycle. 0b1 When enabled, PMCCNTR_EL0 counts once every 64 clock cycles. AU When FEAT_AA32 is implemented 3 3 3 Reserved, RES0. Otherwise C 2 2 2 Cycle counter reset. The effects of writing to this field are: Resetting PMCCNTR_EL0 does not change the cycle counter overflow field. The value of PMCR_EL0.LC is ignored, and bits [63:0] of the cycle counter are reset. 0b0 No action. 0b1 Reset PMCCNTR_EL0 to zero. WO/RAZ P 1 1 1 Event counter reset. The event counters affected by this field are: All event counters in the first range. If any of the following are true, all event counters in the second range: EL2 is disabled or not implemented in the current Security state. The PE is executing at EL2 or EL3. Writes to this field do not affect other event counters, the cycle counter PMCCNTR_EL0, or the instruction counter PMICNTR_EL0. For more information about event counter ranges, see MDCR_EL2.HPMN. Resetting the event counters does not change the event counter overflow fields. If FEAT_PMUv3p5 is implemented, the values of MDCR_EL2.HLP and PMCR_EL0.LP are ignored, and bits [63:0] of all affected event counters are reset. 0b0 No action. 0b1 Reset all affected event counters PMEVCNTR<n>_EL0 to zero. WO/RAZ E 0 0 0 Enable. The counters affected by this field are: The event counters in the first range. For more information about event counter ranges, see MDCR_EL2.HPMN. If FEAT_PMUv3_ICNTR is implemented, the instruction counter PMICNTR_EL0. The cycle counter PMCCNTR_EL0. Other event counters are not affected by this field. 0b0 Affected counters are disabled and do not count. 0b1 Affected counters are enabled by PMCNTENSET_EL0. '0' MRS <Xt>, PMCR_EL0 if !(IsFeatureImplemented(FEAT_PMUv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif PMUSERENR_EL0().EN == '0' || (IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0().UEN == '1') then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPMCR == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMCR_EL0(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPMCR == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMCR_EL0(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMCR_EL0(); end; elsif PSTATE.EL == EL3 then X{64}(t) = PMCR_EL0(); end; MSR PMCR_EL0, <Xt> if !(IsFeatureImplemented(FEAT_PMUv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif PMUSERENR_EL0().EN == '0' || (IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0().UEN == '1') then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMCR_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPMCR == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMCR_EL0() = X{64}(t); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMCR_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPMCR == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMCR_EL0() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMCR_EL0() = X{64}(t); end; elsif PSTATE.EL == EL3 then PMCR_EL0() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel