PMICNTSVR_EL1 Performance Monitors Instruction Count Saved Value Register when FEAT_PMUv3_ICNTR is implemented, FEAT_PMUv3_SS is implemented, and FEAT_AA64 is implemented PMICNTSVR_EL1 Architectural External 63 0 63 0 63 0 63 0 Captures the PMU Instruction counter, PMICNTR_EL0. Unknown PMICNTSVR_EL1 is a 64-bit register. ICNT 63 0 63:0 Sampled Instruction Count. The value of PMICNTR_EL0 at the last successful Capture event. AU AU MRS <Xt>, PMICNTSVR_EL1 if !(IsFeatureImplemented(FEAT_PMUv3_ICNTR) && IsFeatureImplemented(FEAT_PMUv3_SS) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPMSS == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGRTR2_EL2().nPMSSDATA == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPMSS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMICNTSVR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPMSS == '0' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().EnPMSS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMICNTSVR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = PMICNTSVR_EL1(); end; 2026-03-26 20:27:25 2026-03_rel