PMSCR_EL1 Statistical Profiling Control Register (EL1) when FEAT_SPE is implemented Provides EL1 controls for Statistical Profiling. SPE PMSCR_EL1 is a 64-bit register. 63 12 63:12 Reserved, RES0. EnVM 11 11 0 Reserved for software use in nested virtualization. See also PMSCR_EL2.EnVM. AU When FEAT_SPE_nVM is implemented and FEAT_NV is implemented 11 11 11 Reserved, RES0. Otherwise KE 10 10 0 Kernel exception enable for SPE Profiling exceptions taken to EL1. 0b0 SPE Profiling exceptions taken to EL1 are always masked at EL1. 0b1 Enabled SPE Profiling exceptions taken to EL1 are masked at EL1 when PSTATE.PM is 1 and unmasked when PSTATE.PM is 0. AU When FEAT_SPE_EXC is implemented 10 10 10 Reserved, RES0. Otherwise EE 9 8 1:0 Exception Enable. For more information on the values reserved for software use in nested virtualization, see PMSCR_EL2.EE. If the Effective value of PMSCR_EL2.EE is 0b00, then the Effective value of PMSCR_EL1.EE is 0b00. 0b00 Disabled. SPE Profiling exceptions for EL1 are disabled. All of the following apply: Unless enabled by a higher Exception level, SPE Profiling exceptions are not generated. PMBSR_EL1.S drives the interrupt request signal PMBIRQ. Accesses to PMBSR_EL1 at EL1 ignore the value of HCR_EL2.NV1. 0b01 Reserved for software use in nested virtualization. Behaves as 0b00 for the purpose of controlling the SPE Profiling exception and interrupt request signal PMBIRQ, and as 0b11 for the purpose of accesses to PMBSR_EL1. When FEAT_NV is implemented 0b10 Reserved for software use in nested virtualization. Behaves as 0b11 for the purposes of controlling the SPE Profiling exception and interrupt request signal PMBIRQ, and accesses to PMBSR_EL1. When FEAT_NV is implemented 0b11 Enabled. SPE Profiling exceptions for EL1 are enabled, as follows: All Profiling Buffer management events are recorded in PMBSR_EL1, unless they are configured to be recorded in PMBSR_EL3 by MDCR_EL3.PMSEE or PMBSR_EL2 by PMSCR_EL2.EE. SPE Profiling exceptions are generated and taken to EL1 when unmasked and PMBSR_EL1.S is 1, unless the Effective value of HCR_EL2.TGE is 1, in which case the exception is taken to EL2. The interrupt request signal PMBIRQ is not asserted. '00' AU When FEAT_SPE_EXC is implemented 9 8 9:8 Reserved, RES0. Otherwise PCT 7 6 1:0 Physical Timestamp. If timestamp sampling is enabled and the Profiling Buffer owning Exception level is EL1, requests which timestamp counter value is collected. If FEAT_ECV is implemented, this is a two-bit field as shown. Otherwise, bit[7] is RES0. When EL2 is implemented, all of the following apply: If the Profiling Buffer owning Exception level is EL1 and EL2 is enabled in the owning Security state, then the value of PMSCR_EL2.PCT might override or modify the meaning of this field. If the Profiling Buffer owning Exception level is EL2, then this field is ignored by the PE. 0b00 Virtual timestamp. The collected timestamp is the physical counter minus the value of CNTVOFF_EL2. 0b01 Physical timestamp. The collected timestamp is the physical counter. 0b11 Guest physical timestamp. The collected timestamp is the physical counter minus a physical offset. If any of the following are true, the physical offset is zero, otherwise the physical offset is the value of CNTPOFF_EL2: SCR_EL3.ECVEn == 0. CNTHCTL_EL2.ECV == 0. FEAT_ECV_POFF is not implemented. When FEAT_ECV is implemented AU When EL2 is implemented PCT 7 6 1:0 Physical Timestamp. Reserved. This field reads as 0b01 and ignores writes. Software should treat this field as UNK/SBZP. When EL2 is not implemented, the Effective values of CNTVOFF_EL2 and CNTPOFF_EL2 are zero, meaning the virtual counter and physical counter have the same value. Otherwise TS 5 5 5 Timestamp sample enable. Enables recording of a Timestamp packet when the owning Exception level is EL1. If the Profiling Buffer owning Exception level is EL2, then this field is ignored by the PE. For more information, see 'Controlling the data that is collected'. 0b0 Timestamp packet recording disabled. 0b1 Timestamp packet recording enabled. AU PA 4 4 4 Physical Address sample enable. When EL2 is implemented, all of the following apply: If the Profiling Buffer owning Exception level is EL1, then this field is combined with the Effective value PMSCR_EL2.PA to determine whether Physical addresses are collected. If the Profiling Buffer owning Exception level is EL2, then this field is ignored by the PE. For more information, see 'Controlling the data that is collected'. 0b0 Physical addresses are not collected. 0b1 Physical addresses are collected. AU CX 3 3 3 CONTEXTIDR_EL1 sample enable. Enables recording of a Context packet containing the value of CONTEXTIDR_EL1. The PE ignores the value of this field and CONTEXTIDR_EL1 is not recorded when any of the following apply: The sampled operation executes at EL2. The sampled operation executes at EL0 and the Effective value of HCR_EL2.TGE is 1. For more information, see 'Controlling the data that is collected'. 0b0 CONTEXTIDR_EL1 recording disabled. 0b1 CONTEXTIDR_EL1 recording enabled. AU 2 2 2 Reserved, RES0. E1SPE 1 1 1 EL1 Statistical Profiling Enable. If the Effective value of HCR_EL2.TGE is 1, then this field is ignored by the PE. 0b0 Sampling disabled at EL1. 0b1 Sampling enabled at EL1. AU E0SPE 0 0 0 EL0 Statistical Profiling Enable. Controls sampling at EL0 when the Effective value of HCR_EL2.TGE is 0 or if EL2 is disabled or not implemented. If the Effective value of HCR_EL2.TGE is 1, then this field is ignored by the PE. 0b0 Sampling disabled at EL0. 0b1 Sampling enabled at EL0. AU MRS <Xt>, PMSCR_EL1 if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMSCR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPMS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x828); else X{64}(t) = PMSCR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = PMSCR_EL2(); else X{64}(t) = PMSCR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = PMSCR_EL1(); end; MSR PMSCR_EL1, <Xt> if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMSCR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPMS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x828) = X{64}(t); else PMSCR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then PMSCR_EL2() = X{64}(t); else PMSCR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then PMSCR_EL1() = X{64}(t); end; MRS <Xt>, PMSCR_EL12 When FEAT_VHE is implemented if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x828); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMSCR_EL1(); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = PMSCR_EL1(); else Undefined(); end; end; MSR PMSCR_EL12, <Xt> When FEAT_VHE is implemented if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x828) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMSCR_EL1() = X{64}(t); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then PMSCR_EL1() = X{64}(t); else Undefined(); end; end; 2026-03-26 20:27:25 2026-03_rel