PMSFCR_EL1 Sampling Filter Control Register when FEAT_SPE is implemented Controls sample filtering. The filter is the logical AND of the filters controlled by FDS, FnE, FL, FT, and FE bits. For example, if PMSFCR_EL1.FE is 1 and PMSFCR_EL1.FT is 1, then only samples including the selected types and the selected events will be recorded. SPE PMSFCR_EL1 is a 64-bit register. 63 53 63:53 Reserved, RES0. TYPEm 52 48 52:48 When FEAT_SPE_EFT is implemented SIMDm 4 4 4 SIMD filter mask. This field is ignored by the PE when PMSFCR_EL1.FT is 0. 0b0 PMSFCR_EL1.SIMD controls whether SIMD operations are recorded as part of a Boolean-OR filter with other masked operation type filter controls. 0b1 PMSFCR_EL1.SIMD controls whether SIMD operations are recorded as part of a Boolean-AND filter with other unmasked operation type filter controls. AU FPm 3 3 3 Floating-point filter mask. This field is ignored by the PE when PMSFCR_EL1.FT is 0. 0b0 PMSFCR_EL1.FP controls whether floating-point operations are recorded as part of a Boolean-OR filter with other masked operation type filter controls. 0b1 PMSFCR_EL1.FP controls whether floating-point operations are recorded as part of a Boolean-AND filter with other unmasked operation type filter controls. AU STm 2 2 2 Store filter mask. This field is ignored by the PE when PMSFCR_EL1.FT is 0. 0b0 PMSFCR_EL1.ST controls whether store operations are recorded as part of a Boolean-OR filter with other masked operation type filter controls. 0b1 PMSFCR_EL1.ST controls whether store operations are recorded as part of a Boolean-AND filter with other unmasked operation type filter controls. AU LDm 1 1 1 Load filter mask. This field is ignored by the PE when PMSFCR_EL1.FT is 0. 0b0 PMSFCR_EL1.LD controls whether load operations are recorded as part of a Boolean-OR filter with other masked operation type filter controls. 0b1 PMSFCR_EL1.LD controls whether load operations are recorded as part of a Boolean-AND filter with other unmasked operation type filter controls. AU Bm 0 0 0 Branch filter mask. This field is ignored by the PE when PMSFCR_EL1.FT is 0. 0b0 PMSFCR_EL1.B controls whether branch operations are recorded as part of a Boolean-OR filter with other masked operation type filter controls. 0b1 PMSFCR_EL1.B controls whether branch operations are recorded as part of a Boolean-AND filter with other unmasked operation type filter controls. AU When FEAT_SPE_EFT is implemented When FEAT_SPE_EFT is not implemented 4 0 4:0 Reserved, RES0. When FEAT_SPE_EFT is not implemented 47 21 47:21 Reserved, RES0. TYPE 20 16 20:16 SIMD 4 4 0 SIMD filter enable. This field is ignored by the PE and no records are removed by this filter when any of the following apply: PMSFCR_EL1.FT is 0. PMSFCR_EL1.SIMDm is 0 and the values of the PMSFCR_EL1.{SIMD, FP, ST, LD, B} bits for which the corresponding PMSFCR_EL1.{SIMDm, FPm, STm, LDm, Bm} bit is zero are all zero. For filtering purposes, SIMD operations means all Advanced SIMD, SVE, and SME SIMD operations. 0b0 If PMSFCR_EL1.SIMDm is 1, then record only operations that are not SIMD operations. Otherwise, do not record SIMD operations, unless allowed by another operation type filter. 0b1 If PMSFCR_EL1.SIMDm is 1, then record only operations that are SIMD operations. Otherwise, record all SIMD operations. AU When FEAT_SPE_EFT is implemented 4 4 4 Reserved, RES0. Otherwise FP 3 3 0 Floating-point filter enable. This field is ignored by the PE and no records are removed by this filter when any of the following apply: PMSFCR_EL1.FT is 0. PMSFCR_EL1.FPm is 0 and the values of the PMSFCR_EL1.{SIMD, FP, ST, LD, B} bits for which the corresponding PMSFCR_EL1.{SIMDm, FPm, STm, LDm, Bm} bit is zero are all zero. For filtering purposes, floating-point operations means all scalar, Advanced SIMD, SVE, and SME floating-point operations, as defined by the FP_SPEC event. 0b0 If PMSFCR_EL1.FPm is 1, then record only operations that are not floating-point operations. Otherwise, do not record floating-point operations, unless allowed by another operation type filter. 0b1 If PMSFCR_EL1.FPm is 1, then record only operations that are floating-point operations. Otherwise, record all floating-point operations. AU When FEAT_SPE_EFT is implemented 3 3 3 Reserved, RES0. Otherwise ST 2 2 2 Store filter enable. This field is ignored by the PE and no records are removed by this filter when any of the following apply: PMSFCR_EL1.FT is 0. FEAT_SPE_EFT is implemented, PMSFCR_EL1.STm is 0, and the values of the PMSFCR_EL1.{SIMD, FP, ST, LD, B} bits for which the corresponding PMSFCR_EL1.{SIMDm, FPm, STm, LDm, Bm} bit is zero are all zero. For filtering purposes, store operations includes vector stores and all atomic operations. 0b0 If FEAT_SPE_EFT is implemented and PMSFCR_EL1.STm is 1, then record only operations that are not store operations. Otherwise, do not record store operations, unless allowed by another operation type filter. 0b1 If FEAT_SPE_EFT is implemented and PMSFCR_EL1.STm is 1, then record only operations that are store operations. Otherwise, record all store operations. AU LD 1 1 1 Load filter enable. This field is ignored by the PE and no records are removed by this filter when any of the following apply: PMSFCR_EL1.FT is 0. FEAT_SPE_EFT is implemented, PMSFCR_EL1.LDm is 0, and the values of the PMSFCR_EL1.{SIMD, FP, ST, LD, B} bits for which the corresponding PMSFCR_EL1.{SIMDm, FPm, STm, LDm, Bm} bit is zero are all zero. For filtering purposes, load operations includes vector loads and atomic operations that return a value to the PE. 0b0 If FEAT_SPE_EFT is implemented and PMSFCR_EL1.LDm is 1, then record only operations that are not load operations. Otherwise, do not record load operations, unless allowed by another operation type filter. 0b1 If FEAT_SPE_EFT is implemented and PMSFCR_EL1.LDm is 1, then record only operations that are load operations. Otherwise, record all load operations. AU B 0 0 0 Branch filter enable. This field is ignored by the PE and no records are removed by this filter when any of the following apply: PMSFCR_EL1.FT is 0. FEAT_SPE_EFT is implemented, PMSFCR_EL1.Bm is 0, and the values of the PMSFCR_EL1.{SIMD, FP, ST, LD, B} bits for which the corresponding PMSFCR_EL1.{SIMDm, FPm, STm, LDm, Bm} bit is zero are all zero. For filtering purposes, branch operations includes exception returns. 0b0 If FEAT_SPE_EFT is implemented and PMSFCR_EL1.Bm is 1, then record only operations that are not branch operations. Otherwise, do not record branch operations. 0b1 If FEAT_SPE_EFT is implemented and PMSFCR_EL1.Bm is 1, then record only operations that are branch operations. Otherwise, record all branch operations. AU 15 5 15:5 Reserved, RES0. FDS 4 4 0 Filter by Data Source. If PMSFCR_EL1.FDS is 1 and PMSDSFR_EL1 is zero, then no load operations with a Data Source will be recorded. Load operations without a Data Source and other sampled operations are unaffected by this field. 0b0 Data Source filtering disabled. 0b1 Data Source filtering enabled. Samples of load instructions reporting a Data Source not selected by PMSDSFR_EL1 will not be recorded. AU When FEAT_SPE_FDS is implemented 4 4 4 Reserved, RES0. Otherwise FnE 3 3 0 Filter by event, inverted. If any of the following are true, then for each sampled operation, it is CONSTRAINED UNPREDICTABLE whether the sample is discarded or the PE behaves as if PMSFCR_EL1.FnE is 0: PMSFCR_EL1.FnE is 1 and PMSNEVFR_EL1 is zero. PMSFCR_EL1.FnE is 1, PMSFCR_EL1.FE is 1, and there exists a value x such that PMSEVFR_EL1.E[x] is 1 and PMSNEVFR_EL1.E[x] is 1. 0b0 Inverted event filtering disabled. 0b1 Inverted event filtering enabled. Samples including the events selected by PMSNEVFR_EL1 will not be recorded. AU When FEAT_SPE_FnE is implemented 3 3 3 Reserved, RES0. Otherwise FL 2 2 2 Filter by latency. If PMSFCR_EL1.FL is 1 and PMSLATFR_EL1.MINLAT is zero, then for each sampled operation, it is CONSTRAINED UNPREDICTABLE whether the sample is discarded or the PE behaves as if PMSFCR_EL1.FL is 0. 0b0 Latency filtering disabled. 0b1 Latency filtering enabled. Samples with a total latency less than PMSLATFR_EL1.MINLAT will not be recorded. AU FT 1 1 1 Filter by type. The filter is controlled by the TYPE and, if FEAT_SPE_EFT is implemented, TYPEm fields. Type filtering filters according to the type of the sampled operation. If FEAT_SPE_EFT is not implemented, PMSFCR_EL1.FT is 1, and the PMSFCR_EL1.{ST, LD, B} bits are all zero, then for each sampled operation, it is CONSTRAINED UNPREDICTABLE whether the sample is discarded or the PE behaves as if PMSFCR_EL1.FT is 0. For more information, see Filtering by operation type. 0b0 Type filtering disabled. 0b1 Type filtering enabled. Samples not one of the selected types will not be recorded. AU FE 0 0 0 Filter by event. If any of the following are true, then for each sampled operation, it is CONSTRAINED UNPREDICTABLE whether the sample is discarded or the PE behaves as if PMSFCR_EL1.FE is 0: PMSFCR_EL1.FE is 1 and PMSEVFR_EL1 is zero. FEAT_SPE_FnE is implemented, PMSFCR_EL1.FnE is 1, PMSFCR_EL1.FE is 1, and there exists a value x such that PMSEVFR_EL1.E[x] is 1 and PMSNEVFR_EL1.E[x] is 1. 0b0 Event filtering disabled. 0b1 Event filtering enabled. Samples not including the events selected by PMSEVFR_EL1 will not be recorded. AU MRS <Xt>, PMSFCR_EL1 if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMSFCR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPMS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMSFCR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMSFCR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = PMSFCR_EL1(); end; MSR PMSFCR_EL1, <Xt> if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMSFCR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPMS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMSFCR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMSFCR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then PMSFCR_EL1() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel