PMSICR_EL1 Sampling Interval Counter Register when FEAT_SPE is implemented Software must write zero to PMSICR_EL1 before enabling sample profiling for a sampling session. Software must then treat PMSICR_EL1 as an opaque, 64-bit, read/write register used for context switches only. SPE The value of PMSICR_EL1 does not change whilst profiling is disabled. PMSICR_EL1 is a 64-bit register. ECOUNT 63 56 7:0 Secondary sample interval counter. Provides the secondary counter used after the primary counter reaches zero. While the secondary counter is nonzero and profiling is enabled, the secondary counter decrements by 1 for each member of the sample population. The primary counter also continues to decrement since it is also nonzero. When the secondary counter reaches zero, a member of the sampling population is selected for sampling. AU When FEAT_SPE_ERnd is implemented 63 56 63:56 Reserved, RES0. Otherwise 55 32 55:32 Reserved, RES0. COUNT 31 0 31:0 Primary sample interval counter. Provides the primary counter used for sampling. When the PE moves from a state or Exception level where profiling is disabled to a state or Exception level where profiling is enabled, if the value of this register is zero, then the primary counter is loaded from PMSIRR_EL1. While the primary counter is nonzero and sampling is enabled, the primary counter decrements by 1 for each member of the sample population. The sample interval counter counts either a number of operations or a number of instructions, depending on the IMPLEMENTATION DEFINED value of PMSIDR_EL1.ArchInst. When the counter reaches zero, the behavior depends on the value of PMSIRR_EL1.RND and whether FEAT_SPE_ERnd is implemented: If PMSIRR_EL1.RND is 1 and FEAT_SPE_ERnd is implemented, then the secondary counter is set to a random or pseudorandom value in the range 0x00 to 0xFF. Otherwise, a member of the sampling population is selected for sampling. The primary counter is loaded from PMSIRR_EL1. The primary counter is loaded from PMSIRR_EL1 means: PMSICR_EL1.COUNT[31:8] is set to the value of PMSIRR_EL1.INTERVAL. If PMSIRR_EL1.RND is 1 and FEAT_SPE_ERnd is not implemented, then PMSICR_EL1.COUNT[7:0] is set to a random or pseudorandom value in the range 0x00 to 0xFF. Otherwise, PMSICR_EL1.COUNT[7:0] is set to 0x00. For more information, see Initializing the sample interval counters and Behavior of the sample interval counter while profiling is enabled. AU MRS <Xt>, PMSICR_EL1 if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMSICR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPMS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x838); else X{64}(t) = PMSICR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMSICR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = PMSICR_EL1(); end; MSR PMSICR_EL1, <Xt> if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMSICR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPMS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x838) = X{64}(t); else PMSICR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMSICR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then PMSICR_EL1() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel