PMSIDR_EL1 Sampling Profiling ID Register when FEAT_SPE is implemented Describes the Statistical Profiling implementation to software. Identification Registers PMSIDR_EL1 is a 64-bit register. 63 33 63:33 Reserved, RES0. SME 32 32 32 SPE for SME. Describes support for the Scalable Matrix Extensions to Statistical Profiling. FEAT_SPE_SME implements the functionality identified by the value 1. 0b0 The SME extensions to the Statistical Profiling Extension are not implemented. 0b1 Adds support for Statistical Profiling of the Scalable Matrix Extensions. RO ALTCLK 31 28 31:28 Alternate clock domain. All other values are reserved. FEAT_SPE_ALTCLK implements the functionality identified by a nonzero value. 0b0000 Alternate clock domain not implemented, or CPU clock domain. 0b0001 The external Streaming Mode Compute Unit provides the alternate clock domain. 0b1111 IMPLEMENTATION DEFINED clock domain. RO FPF 27 27 27 Floating-point flag. Describes whether Operation Type packets for sampled scalar and SIMD operations contain floating-point and Advanced SIMD indications. FEAT_SPE_FPF implements the functionality identified by the value 1. 0b0 Operation Type packets for scalar and Advanced SIMD operations do not contain floating-point or Advanced SIMD information. 0b1 Operation Type packets for scalar and Advanced SIMD operations contain floating-point or Advanced SIMD information. RO EFT 26 26 26 Extended filtering by type. Describes whether Extended filtering by operation type is supported. FEAT_SPE_EFT implements the functionality identified by the value 1. 0b0 PMSFCR_EL1.{SIMDm, FPm, STm, Bm, LDm, SIMD, FP} are RES0. 0b1 PMSFCR_EL1.{SIMDm, FPm, STm, Bm, LDm, SIMD, FP} are implemented. RO CRR 25 25 25 Call Return branch records. Describes whether the Operation Type packets for sampled branch operations contain Call Return information. FEAT_SPE_CRR implements the functionality identified by the value 1. 0b0 Operation Type packets for branch operations do not contain Call Return information. 0b1 Operation Type packets for branch operations contain Call Return information. RO PBT 24 24 24 Previous branch target Address packet. Describes whether the Previous branch target Address packet is supported. FEAT_SPE_PBT implements the OPTIONAL functionality identified by the value 1. 0b0 Previous branch target Address packet not implemented. 0b1 Previous branch target Address packet implemented. RO Format 23 20 23:20 Defines the format of the sample records. All other values are reserved. 0b0000 Format 0. RO CountSize 19 16 19:16 Defines the size of the counters. All other values are reserved. 0b0010 12-bit saturating counters. 0b0011 16-bit saturating counters. RO MaxSize 15 12 15:12 Defines the largest size for a single record, rounded up to a power-of-two. If this is the same as the minimum alignment (PMBIDR_EL1.Align), then each record is exactly this size. All other values are reserved. The values 0b0100 and 0b0101 are not permitted for an implementation. 0b0100 16 bytes. 0b0101 32 bytes. 0b0110 64 bytes. 0b0111 128 bytes. 0b1000 256 bytes. 0b1001 512 bytes. 0b1010 1KB. 0b1011 2KB. RO Interval 11 8 11:8 Minimum sampling interval. This provides guidance from the implementer to the smallest sampling interval. The interval is defined as a number of either operations or instructions, depending on the IMPLEMENTATION DEFINED value of PMSIDR_EL1.ArchInst. All other values are reserved. If this field reads as a nonzero value, then setting the sample interval to a value less than the indicated value is likely to cause a statistically significant number of sample collisions. For example, the smallest interval might indicate the typical size of the speculation window for the implementation. That is, the number of operations or instructions that will be executing in parallel, when the processor implementation is not heavily loaded. Setting the sample interval to a value greater than or equal to the indicated value does not guarantee a statistically insignificant number of sample collisions, as this is typically dependent on the program being profiled. For example, if the program has a large number of long latency loads due to cache misses, then this might cause more collisions when these operations or instructions are sampled. For more information, see 'Sample collisions'. 0b0000 256 operations or instructions, or no minimum specified. 0b0010 512 operations or instructions. 0b0011 768 operations or instructions. 0b0100 1,024 operations or instructions. 0b0101 1,536 operations or instructions. 0b0110 2,048 operations or instructions. 0b0111 3,072 operations or instructions. 0b1000 4,096 operations or instructions. RO FDS 7 7 0 Filtering by data source. FEAT_SPE_FDS implements the functionality identified by the value 1. From Armv8.9, if FEAT_SPE_LDS is implemented, the value 0 is not permitted. 0b0 PMSDSFR_EL1 is not implemented and PMSFCR_EL1.FDS is RES0. 0b1 PMSDSFR_EL1 and PMSFCR_EL1.FDS are implemented. RO When FEAT_SPEv1p4 is implemented 7 7 7 Reserved, RES0. Otherwise FnE 6 6 0 Filtering by events, inverted. FEAT_SPE_FnE implements the functionality identified by the value 1. From Armv8.7, if FEAT_SPE is implemented, the value 0 is not permitted. 0b0 PMSNEVFR_EL1 is not implemented and PMSFCR_EL1.FnE is RES0. 0b1 PMSNEVFR_EL1 and PMSFCR_EL1.FnE are implemented. RO When FEAT_SPE_FnE is implemented 6 6 6 Reserved, RES0. Otherwise ERnd 5 5 5 Defines how the random number generator is used in determining the interval between samples, when enabled by PMSIRR_EL1.RND. FEAT_SPE_ERnd implements the functionality identified by the value 1. 0b0 The random number is added at the start of the interval, and the sample is taken and a new interval started when the combined interval expires. 0b1 The random number is added and the new interval started after the interval programmed in PMSIRR_EL1.INTERVAL expires, and the sample is taken when the random interval expires. RO LDS 4 4 4 Data source indicator for sampled load instructions. FEAT_SPE_LDS implements the functionality identified by the value 1. 0b0 Loaded data source not implemented. 0b1 Loaded data source implemented. RO ArchInst 3 3 3 Architectural instruction profiling. Defines the subject of the profiling population. FEAT_SPE_ArchInst implements the functionality identified by the value 1. 0b0 Micro-op sampling implemented. 0b1 Architecture instruction sampling implemented. RO FL 2 2 2 Filtering by latency. Reads as 0b1. RO FT 1 1 1 Filtering by operation type. Reads as 0b1. RO FE 0 0 0 Filtering by events. Reads as 0b1. RO MRS <Xt>, PMSIDR_EL1 if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMSIDR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPMS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMSIDR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMSIDR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = PMSIDR_EL1(); end; 2026-03-26 20:27:25 2026-03_rel