PMSWINC_EL0 Performance Monitors Software Increment Register when FEAT_PMUv3 is implemented and FEAT_AA64 is implemented PMSWINC Architectural AArch32 31 0 31 0 31 0 31 0 PMSWINC_EL0 Architectural External 31 0 31 0 31 0 31 0 when FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3p9 is not implemented Increments a counter that is configured to count the Software increment event, event 0x00. For more information, see 'SW_INCR'. PMU PMSWINC_EL0 is a 64-bit register. 63 31 63:31 Reserved, RES0. P<m> 30 0 30:0 Software increment. 30 0 0b0 Write is ignored. 0b1 Increment PMEVCNTR<m>_EL0, if PMEVCNTR<m>_EL0 is configured to count software increment events. When m >= GetNumEventCountersAccessible() RAZ/WI FEAT_PMUv3p9 is implemented EL0 is the current Exception level PMUSERENR_EL0.[UEN,SW] == '10' PMUACR_EL1.P<m> == '0' RAZ/WI WO/RAZ MSR PMSWINC_EL0, <Xt> if !(IsFeatureImplemented(FEAT_PMUv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif (IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0().[UEN,SW,EN] == '000') || (!IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0().[SW,EN] == '00') then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMSWINC_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMSWINC_EL0() = X{64}(t); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMSWINC_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMSWINC_EL0() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMSWINC_EL0() = X{64}(t); end; elsif PSTATE.EL == EL3 then PMSWINC_EL0() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel